This task deepens your understanding of how transistor-level circuit properties (device physics, sizing, variation) drive the timing behavior that STA analyzes. By working through CMOS design and SPICE simulations (as in the sky130 workshop), you will see the “real” side of what STA approximates. This strengthens your intuition about slack, delay, noise margins, and variation impacts.
Download workshop Collaterals from below link https://github.com/kunalg123/sky130CircuitDesignWorkshop/
| Day | Description |
|---|---|
| 🗓️ Day 1 | CMOS Circuit Design and SPICE Simulations. |
| 🗓️ Day 2 | Velocity Saturation and basics of CMOS inverter VTC. |
| 🗓️ Day 3 | CMOS Switching threshold and dynamic simulations |
| 🗓️ Day 4 | Static Behavior Evaluation: CMOS Inverter Robustness and Noise Margin |
| 🗓️ Day 5 | CMOS power supply and device variation robustness evaluation |
Author: coder7676mit
Project: RISC-V Tapeout 2025 – Week 4 (SPICE Simulation)