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coder7676mit/README.md

Nagendra Kudva

ECE Sophomore at MIT Manipal | Digital & Analog VLSI | FPGA & RISC-V Systems

I am a second-year Electronics and Communication Engineering student at MIT Manipal. My interests focus on digital IC design, RTL development in Verilog, FPGA-based systems, and analog VLSI research. I am currently working on RISC-V processor design flows using open-source tools (OpenROAD) and exploring FPGA implementations and transistor-level circuit analysis. My focus is on building strong fundamentals in digital electronics, computer architecture, and VLSI design, with emphasis on synthesizable RTL and practical hardware understanding.

Selected Repositories

Repository Description Core Concepts Technologies
MIPS32-Processor-RTL 5-stage pipelined MIPS processor Pipeline architecture, R/I/J instructions, RTL design Verilog
RISC-V Flow Setup Open-source RISC-V design flow setup using OpenROAD ASIC flow, synthesis, placement & routing Verilog, OpenROAD
UART Tx-Rx Verilog based UART transmitter abd reciever UART and its peripharals Xilinx Vivado, Verilog, FPGA

Technical Background

Area Details
Digital Design RTL in Verilog, FSMs, timing-aware logic
Chip & FPGA Design RTL-to-synthesis flow, FPGA implementation, timing verification
Analog VLSI design Cadence Virtuoso, Transistor-level schematic design, SPICE simulations, post-layout analysis

Languages and Tools

  • Programming: Python, C /C++
  • Hardware / VLSI: Verilog, FPGA, Cadence Virtuoso, SPICE simulation, Xilinx Vivado.
  • Open-Source Tools: OpenROAD/Openlane, RISC-V toolchain.

Popular repositories Loading

  1. MIPS32-Processor-RTL MIPS32-Processor-RTL Public

    Verilog 1

  2. nkvlsiRisc-V-tapeout-vsd nkvlsiRisc-V-tapeout-vsd Public

  3. RiscV_tapeout_2025_RTL_week1 RiscV_tapeout_2025_RTL_week1 Public

    Week 1 of the vsd 2025 tapeout program, i.e, RTL design and synthesis using sky130

  4. RiscV_tapeout_2025_week2_SoC RiscV_tapeout_2025_week2_SoC Public

  5. RiscV_tapeout_2025_week3_OpenSTA RiscV_tapeout_2025_week3_OpenSTA Public

  6. RiscV_tapeout_2025_week4_SPICE RiscV_tapeout_2025_week4_SPICE Public