CPU Benchmarks Set
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Jul 25, 2024 - C
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dhrystone
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🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.
computer-science cpu fpga processor riscv verilog computer-architecture hdl soc verilog-hdl risc-v soft-core rv32i system-on-chip riscv32 dhrystone rv32 processor-design basic-rv32s risc-v-learn
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Feb 2, 2026 - Verilog
LEVEL: Open-source RV32IMC RISC-V processor core with pipelined microarchitecture, cache support, SoC peripherals and verification framework.
gpio i2c cache riscv rtl spi csr uart systemverilog yosys coremark verilator wishbone-bus vga-controller dhrystone gshare 5-stage-pipelined-processor embench-iot imperas risc-v-dv
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Apr 6, 2026 - SystemVerilog
Benchmarks set written in C#, Java, PHP, JS, Python, Lua, Go
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Sep 30, 2025 - Lua
A 6-Stage RISC-V RV32IM Core on FPGA (263.7 CoreMark, 91.0 DMIPS@100MHz)
cpu fpga runtime architecture riscv verilog uart systemverilog hdl microarchitecture branch-prediction coremark rv32i cpu-architecture dhrystone rv32im uart-programming
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Mar 11, 2026 - SystemVerilog
This work presents the design and implementation of high performance and low power 32-bit RISC-V processor 4-stage pipelined for non-load and 5-stage for load operations, also extending its capabilities as system on chip (SoC) design. RV32I with M extension designed for FPGA and ASIC
asic fpga pipeline processor embedded-systems isa cprogramming risc-v cadence genus coremark rv32i artix7 digitaldesign nexys4ddr dhrystone rv32im innovus systemonchip xilinxvivado
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Mar 28, 2026
Dhrystone Benchmark measurement calculation for complexity of integer computation performed on ESP 32
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Feb 25, 2021 - C++
microcontroller i2c mbed spi led adc stm32f401re uart mutex pwm push-button ds1631 dhrystone keil-uvision nhd-0216hz-fsw-fbw-33v3c
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Oct 25, 2022 - C
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