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add spregfile mapping#210

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gadfort merged 4 commits into
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spregfile
Apr 10, 2026
Merged

add spregfile mapping#210
gadfort merged 4 commits into
mainfrom
spregfile

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@gadfort gadfort commented Apr 10, 2026

Summary by CodeRabbit

  • New Features

    • Extended library support with single-port register file variants for ASAP7, FreePDK45, GF180, IHP130, and Sky130 process technologies. Users now have access to register file memory implementations across all supported PDK ecosystems alongside existing single-port RAM options.
  • Tests

    • Removed a previously deactivated test module.

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ℹ️ Review info
⚙️ Run configuration

Configuration used: defaults

Review profile: CHILL

Plan: Pro

Run ID: ef99cd81-6662-4cf9-8efe-6b44e7c5a65a

📥 Commits

Reviewing files that changed from the base of the PR and between c136c86 and 1962522.

📒 Files selected for processing (5)
  • lambdapdk/asap7/libs/fakeram7.py
  • lambdapdk/freepdk45/libs/fakeram45.py
  • lambdapdk/gf180/libs/gf180sram.py
  • lambdapdk/ihp130/libs/sg13g2_sram.py
  • lambdapdk/sky130/libs/sky130sram.py
📝 Walkthrough

Walkthrough

This PR introduces a new la_spregfile (single-port register file) wrapper module across five process design kits (ASAP7, FreePDK45, GF180, IHP130, Sky130). Each PDK receives a corresponding Python library class and Verilog wrapper module that delegates to the existing la_spram functionality. The main __init__.py is updated to register these new libraries in get_libs().

Changes

Cohort / File(s) Summary
Core Library Registration
lambdapdk/__init__.py
Updated get_libs() to instantiate and return five new *Lambdalib_SinglePortRegfile classes alongside existing single-port RAM entries.
ASAP7 PDK
lambdapdk/asap7/libs/fakeram7.py, lambdapdk/asap7/libs/fakeram7/lambda/la_spregfile.v
Added FakeRAM7Lambdalib_SinglePortRegfile wrapper class and corresponding la_spregfile Verilog module that instantiates la_spram with parameterized memory/control interfaces.
FreePDK45 PDK
lambdapdk/freepdk45/libs/fakeram45.py, lambdapdk/freepdk45/libs/fakeram45/lambda/la_spregfile.v
Added FakeRAM45Lambdalib_SinglePortRegfile wrapper class and la_spregfile Verilog module following the same pattern as ASAP7.
GF180 PDK
lambdapdk/gf180/libs/gf180sram.py, lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda/la_spregfile.v
Added GF180Lambdalib_SinglePortRegfile wrapper class and la_spregfile Verilog module with identical wrapper structure.
IHP130 PDK
lambdapdk/ihp130/libs/sg13g2_sram.py, lambdapdk/ihp130/libs/sg13g2_sram/lambda/la_spregfile.v
Added IHP130Lambdalib_SinglePortRegfile wrapper class and la_spregfile Verilog module with matching wrapper implementation.
Sky130 PDK
lambdapdk/sky130/libs/sky130sram.py, lambdapdk/sky130/libs/sky130sram/lambda/la_spregfile.v
Added Sky130Lambdalib_SinglePortRegfile wrapper class and la_spregfile Verilog module with consistent wrapper pattern.
Test Removal
tests/test_lambda.py
Deleted test file that was already disabled via module-level pytest skip.

Estimated code review effort

🎯 2 (Simple) | ⏱️ ~12 minutes

Possibly related PRs

  • update ramlib impl to use new API #200: Introduces RAM/SPRAM modifications that directly relate to the new FakeRAM7Lambdalib_SinglePortRegfile class and la_spregfile wrapper infrastructure added in this PR.

Poem

🐰 Hop, hop! New regfiles bloom,
Wrapping sprams across the zoom,
Five PDKs dressed in flair,
Lambda's wrappers everywhere!

🚥 Pre-merge checks | ✅ 2 | ❌ 1

❌ Failed checks (1 warning)

Check name Status Explanation Resolution
Docstring Coverage ⚠️ Warning Docstring coverage is 20.00% which is insufficient. The required threshold is 80.00%. Write docstrings for the functions missing them to satisfy the coverage threshold.
✅ Passed checks (2 passed)
Check name Status Explanation
Description Check ✅ Passed Check skipped - CodeRabbit’s high-level summary is enabled.
Title check ✅ Passed The PR title 'add spregfile mapping' accurately describes the main change: adding new single-port register file wrapper classes and modules across multiple PDK libraries.

✏️ Tip: You can configure your own custom pre-merge checks in the settings.

✨ Finishing Touches
🧪 Generate unit tests (beta)
  • Create PR with unit tests
  • Commit unit tests in branch spregfile

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Actionable comments posted: 6

🤖 Prompt for all review comments with AI agents
Verify each finding against the current code and only fix it if needed.

Inline comments:
In `@lambdapdk/asap7/libs/fakeram7.py`:
- Around line 454-455: The continuation indentation for the super().__init__
call is triggering flake8 E128; adjust the call so the second argument is
aligned with the first or indented under the opening parenthesis. For example,
format the invocation of super().__init__("la_spregfile",
FakeRAM7Lambdalib_SinglePort().techlibs) so the
FakeRAM7Lambdalib_SinglePort().techlibs argument is on the same line or properly
indented beneath the opening parenthesis to satisfy flake8; update the
super().__init__ invocation in the class that references "la_spregfile" and
FakeRAM7Lambdalib_SinglePort accordingly.

In `@lambdapdk/freepdk45/libs/fakeram45.py`:
- Around line 154-155: The call to super().__init__ in fakeram45.py currently
has a hanging-indent style that triggers E128; adjust the indentation of the
continuation line so it visually lines up with the opening parenthesis or the
first argument. Specifically, in the call to super().__init__("la_spregfile",
FakeRAM45Lambdalib_SinglePort().techlibs) ensure the second line is indented to
match the position after the opening paren (or align with the first argument) so
the continuation is visually consistent and E128 is resolved.

In `@lambdapdk/gf180/libs/gf180sram.py`:
- Around line 193-194: The constructor call to super().__init__ in the class
containing "la_spregfile" is mis-indented causing E128; fix the indentation so
the second line aligns with the opening parenthesis (or indent one additional
level) for the arguments, e.g. ensure GF180Lambdalib_SinglePort().techlibs is
vertically aligned with "la_spregfile" within the super().__init( ... ) call;
update the super().__init__("la_spregfile",
GF180Lambdalib_SinglePort().techlibs) invocation accordingly to conform to E128
rules.

In `@lambdapdk/ihp130/libs/sg13g2_sram.py`:
- Around line 177-178: The continuation of the super().__init__ call is
misaligned causing flake8 E128; reformat the call to use a proper visual
continuation by placing the opening parenthesis on the first line and aligning
subsequent arguments under it (i.e., break the arguments onto their own indented
lines) for the call to super().__init__ that passes "la_spregfile" and
IHP130Lambdalib_SinglePort().techlibs so the indentation conforms to E128.

In `@lambdapdk/sky130/libs/sky130sram.py`:
- Around line 139-143: The code sets lib_path to Path("lambdapdk", "ihp130",
"libs", "sg13g2_sram") but then registers la_spregfile.v from that IHP130 path,
causing the wrong PDK to be packaged; update lib_path to the correct Sky130 PDK
directory (e.g., Path("lambdapdk", "sky130", "libs", "<appropriate_sram_dir>")
or the actual sky130 regfile path) so that the call self.add_file(lib_path /
"lambda" / "la_spregfile.v") references the Sky130 RTL; adjust the Path
construction where lib_path is defined (and keep surrounding
active_dataroot("lambdapdk") / active_fileset("rtl") / add_file usage intact).
- Around line 132-133: The continuation indentation on the super().__init__ call
for "la_spregfile" is violating flake8 E128; fix it by reformatting the
constructor call so the argument lines use a valid continuation indent (either
place both arguments on one line or put the second argument on the next line
with a hanging indent aligned under the first argument or the opening
parenthesis). Update the super().__init__ invocation that passes "la_spregfile"
and Sky130Lambdalib_SinglePort().techlibs to follow standard continuation-indent
rules so flake8 no longer errors.
🪄 Autofix (Beta)

Fix all unresolved CodeRabbit comments on this PR:

  • Push a commit to this branch (recommended)
  • Create a new PR with the fixes

ℹ️ Review info
⚙️ Run configuration

Configuration used: defaults

Review profile: CHILL

Plan: Pro

Run ID: 28595914-7c03-4edb-9f6e-033427759e98

📥 Commits

Reviewing files that changed from the base of the PR and between c369d33 and c136c86.

📒 Files selected for processing (12)
  • lambdapdk/__init__.py
  • lambdapdk/asap7/libs/fakeram7.py
  • lambdapdk/asap7/libs/fakeram7/lambda/la_spregfile.v
  • lambdapdk/freepdk45/libs/fakeram45.py
  • lambdapdk/freepdk45/libs/fakeram45/lambda/la_spregfile.v
  • lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda/la_spregfile.v
  • lambdapdk/gf180/libs/gf180sram.py
  • lambdapdk/ihp130/libs/sg13g2_sram.py
  • lambdapdk/ihp130/libs/sg13g2_sram/lambda/la_spregfile.v
  • lambdapdk/sky130/libs/sky130sram.py
  • lambdapdk/sky130/libs/sky130sram/lambda/la_spregfile.v
  • tests/test_lambda.py
💤 Files with no reviewable changes (1)
  • tests/test_lambda.py

Comment thread lambdapdk/asap7/libs/fakeram7.py Outdated
Comment thread lambdapdk/freepdk45/libs/fakeram45.py Outdated
Comment thread lambdapdk/gf180/libs/gf180sram.py Outdated
Comment thread lambdapdk/ihp130/libs/sg13g2_sram.py Outdated
Comment thread lambdapdk/sky130/libs/sky130sram.py Outdated
Comment thread lambdapdk/sky130/libs/sky130sram.py Outdated
@gadfort gadfort merged commit 7cfc1e7 into main Apr 10, 2026
4 checks passed
@gadfort gadfort deleted the spregfile branch April 10, 2026 15:28
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