Add optimized AVX2 kernels for csetv and zsetv on AMD Zen architectures#922
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harsdave wants to merge 1 commit intoflame:masterfrom
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Add optimized AVX2 kernels for csetv and zsetv on AMD Zen architectures#922harsdave wants to merge 1 commit intoflame:masterfrom
harsdave wants to merge 1 commit intoflame:masterfrom
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Description: This commit introduces optimized intrinsic-based implementations for bli_csetv_zen_int and bli_zsetv_zen_int. These kernels are designed to leverage AVX2 SIMD instructions for single-precision and double-precision complex vector initialization on AMD Zen/2/3 microarchitectures. Key highlights: Vectorization: Utilizes _mm256_storeu_ps/pd to perform 256-bit wide stores, significantly improving throughput for unit-stride cases (incx == 1). Loop Unrolling: Implements a multi-tiered unrolling strategy (64, 32, 16, 8, 4 for single-precision; 32, 16, 8, 4, 2 for double-precision) to maximize pipeline utilization and reduce loop overhead. Conjugation Support: Correctly handles conjalpha by pre-processing the imaginary component of the alpha value before broadcasting. Fringe Handling: Uses bit-masking logic (n & ~0x3F, etc.) to efficiently process remainders in decreasing powers of two. Performance Safety: Includes _mm256_zeroupper() in the zsetv kernel to mitigate AVX-SSE transition penalties. Stride Support: Maintains a scalar fallback for non-unit stride cases to ensure functional correctness across all inputs.
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Description:
This commit introduces optimized intrinsic-based implementations for bli_csetv_zen_int and bli_zsetv_zen_int. These kernels are designed to leverage AVX2 SIMD instructions for single-precision and double-precision complex vector initialization on AMD Zen/2/3 microarchitectures.
Key highlights:
Vectorization: Utilizes _mm256_storeu_ps/pd to perform 256-bit wide stores, significantly improving throughput for unit-stride cases (incx == 1).
Loop Unrolling: Implements a multi-tiered unrolling strategy (64, 32, 16, 8, 4 for single-precision; 32, 16, 8, 4, 2 for double-precision) to maximize pipeline utilization and reduce loop overhead.
Conjugation Support: Correctly handles conjalpha by pre-processing the imaginary component of the alpha value before broadcasting.
Fringe Handling: Uses bit-masking logic (n & ~0x3F, etc.) to efficiently process remainders in decreasing powers of two.
Performance Safety: Includes _mm256_zeroupper() in the zsetv kernel to mitigate AVX-SSE transition penalties.
Stride Support: Maintains a scalar fallback for non-unit stride cases to ensure functional correctness across all inputs.