A DPI based test framework

[sequencer]

Since verilator 5 supports --timing, makes rocketchip being able to use pure SystemVerilog+DPI tests to align with commercial tools like VCS. This PR adds a demo DPI test framework for illustrating this new methodology.

The new tests aims to speed the test without using JTAG to transfer test binary via DTM. It instantiate a block of AXI bus functional module, which loads elf from plusarg file path.

In the following PRs:

• we can start to migrate RISC-V Tests.
• use Select API in Chisel to select RocketCore and probe from it to add architecture event log.
• fuzz
• based on the event log, check the correctness of test result by difftest with spike.
• create a uArch diagram to demonstrate the pipeline

The current DPI Module is pretty dirty, I know, I will try to find a way to get clean up it with DPI IntModule in Chisel.

Related issue:

Type of change: bug report | feature request | other enhancement

Impact: no functional change | API addition (no impact on existing code) | API modification

Development Phase: proposal | implementation

Release Notes

[poemonsense]

Since verilator 5 supports --timing, makes rocketchip being able to use pure SystemVerilog+DPI tests to align with commercial tools like VCS. This PR adds a demo DPI test framework for illustrating this new methodology.

I think Verilator 4 already supports both pure and non-pure DPI calls. Verilator is able to handle the scheduling issues with single-thread and multithreading.

The new tests aims to speed the test without using JTAG to transfer test binary via DTM. It instantiate a block of AXI bus functional module, which loads elf from plusarg file path.

  private val outer = this

  lazy val module = new Impl
-  class Impl extends LazyModuleImp(this) with HasJustOneSeqMem {
+  class Impl extends LazyModuleImp(this) {
    val (in, edgeIn) = node.in(0)
    val laneDataBits = 8
-    val mem = makeSinglePortedByteWriteSeqMem(
+    val mem = difftest.common.DifftestMem(
      size = BigInt(1) << mask.filter(b=>b).size,
      lanes = beatBytes,
-      bits = laneDataBits)
+      bits = laneDataBits,
+      singlePort = false,
+    )
    val eccCode = None
    val address = outer.address

Like this?

• based on the event log, check the correctness of test result by difftest with spike.

We have a demo at https://github.com/OpenXiangShan/rocket-chip/tree/dev-difftest, being able to cosimulate with Spike. Probably we can work together to improve XS implementation of difftest (https://github.com/OpenXiangShan/difftest) towards your goals. No need to work from scratch for rocket-chip version of difftest.

Dromajo is another choice of co-simulation, though in Verilog.

[sequencer]

The chipsalliance as upstream only accepts Apache, that the problem that rocketchip is unable to adopt the xiangshan's difftest.

I'm drafting a RISC VIP based on Probe API and LTL, maybe we can have some alignment there.

[jerryz123]

Chipyard also has a pure trace-based lockstep cosimulation. Similar to Dromajo but using spike as the functional model.