AArch64 IR instruction fix for rbit instruction and ctr_el0 register#1509
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PerfectLaugh wants to merge 2 commits intocea-sec:masterfrom
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AArch64 IR instruction fix for rbit instruction and ctr_el0 register#1509PerfectLaugh wants to merge 2 commits intocea-sec:masterfrom
rbit instruction and ctr_el0 register#1509PerfectLaugh wants to merge 2 commits intocea-sec:masterfrom
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op2 for ctr_el0 should be 0b11 instead of 0b00 https://developer.arm.com/documentation/ddi0601/2024-12/AArch64-Registers/CTR-EL0--Cache-Type-Register
rbit: Reverse bits in register
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rbitinstruction and fixctr_el0registerhttps://developer.arm.com/documentation/ddi0597/latest/Base-Instructions/RBIT--Reverse-Bits-
https://developer.arm.com/documentation/ddi0601/2024-12/AArch64-Registers/CTR-EL0--Cache-Type-Register