I'm an Electronics & Communications Engineer (ranked 3rd / 90.3% — Excellent with Honors) specializing in ASIC Physical Design and Digital Verification. My work spans the complete RTL-to-GDSII flow using both industry-standard tools (Synopsys Design Compiler, ICC2) and open-source EDA (LibreLane, OpenROAD, Sky130 PDK).
- Research Assistant @ AUC — Leading physical design and tape-out of a 12-slot OpenFrame Multi-Project Chip; teaching the ASIC flow to students and authoring RTL-to-GDSII course modules on ReadTheDocs.
- Digital Verification Intern @ Si-Vision Academy — Building UVM-based verification environments in SystemVerilog with constrained-random testing, SVA assertions, and functional/code coverage.
- Digital Design & FPGA Intern @ STMicroelectronics — Architecting and implementing the convolution engine for an SNN accelerator on Virtex UltraScale+ FPGAs.
- Passionate about timing closure, EDA automation, physical verification, and open-source silicon.
┌─────────────────────────────────────────────────────────────────┐
│ OpenFrame Multi-Project Chip → 12-slot tape-out @ AUC │
│ UVM Verification → Si-Vision Academy │
│ SNN FPGA Accelerator → STMicroelectronics │
└─────────────────────────────────────────────────────────────────┘
| Project | Description | Tools & PDK |
|---|---|---|
| OpenFrame Multi-Project ASIC | Led full RTL-to-GDSII implementation of a 12-slot OpenFrame chip. Custom scripts for macro placement, power networks, and tape-out signoff. | LibreLane · OpenROAD · Sky130 PDK |
| AES Vector RISC-V Processor | End-to-end physical design of a 32-bit RISC-V core with custom AES vector engine. 32nm SAED PDK, 9 metal layers, 200 MHz target. Solved timing via retiming, NDR/CTS scripts, and CCD flow. | Synopsys DC · ICC2 · PrimeTime · SAED 32nm |
| ORCA Processor Physical Implementation | RTL-to-GDSII implementation with multi-voltage domain power architecture. Applied UPF for power gating, isolation cells, and multi-domain PG design. | Synopsys DC · ICC2 · SAED 32nm |
| AES-128 Caravel Integration | Integrated AES core as a macro inside Caravel SoC; achieved full timing closure and resolved all DRC, LVS, and antenna violations. | LibreLane · Sky130 PDK · Caravel |
| AES UVM Verification Environment | Modular constrained-random UVM testbench for AES encryption. Full driver/monitor/scoreboard/coverage model implementation. | SystemVerilog · UVM · QuestaSim |
| SNN Accident Detection Accelerator | Designed convolution engine for SNN-based accident detection — optimized Verilog for high-frequency execution on Virtex UltraScale+. | Verilog · Quartus · Virtex UltraScale+ |
Open to full-time roles and research collaborations in ASIC Physical Design and Digital Verification.
basemhesham159@gmail.com