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1. AC-to-DC-Rectifier-Project AC-to-DC-Rectifier-Project Public

   B.Tech ECE Electronics and devices Lab Project – AC to DC Rectifier with +5V and −5V Output

2. Digital-Clock-Using-7490-7446-555 Digital-Clock-Using-7490-7446-555 Public

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3. Voice-Controlled-Robotic-Car Voice-Controlled-Robotic-Car Public

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4. 4bit-structural-calculator-verilog 4bit-structural-calculator-verilog Public

   Structural Verilog implementation of a 4-bit arithmetic unit supporting addition, subtraction, multiplication, and restoring division with full testbench verification.

5. Synchronous-FIFO Synchronous-FIFO Public

   Parameterized synchronous FIFO implemented in Verilog HDL using circular buffer architecture with full and empty detection, including a complete RTL testbench.

6. FSM-1001-Overlapping-in-verilog- FSM-1001-Overlapping-in-verilog- Public

   Overlapping sequence detector for pattern 1001 implemented using Mealy FSM in Verilog HDL with complete testbench verification.

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