Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a logic simulation. and drive a memory mapped bus

Using Nim to interface with SystemVerilog test benches via DPI-C

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

SystemVerilog implementation of RISC-V RV32IM & custom packed SIMD ISA as 5-stage single-issue CPU core with branch predictor and L1 caches, tied up in lockstep with ISA sim over DPI for verification

C++ Instruction Set Simulator for RISC-V RV32IMC & custom packed SIMD ISA with cache and branch predictor models, C/ASM workloads, and Python analysis tools

Example of DPI-C usage in UVM with Vivado simulator (xsim) and Altair (Metrics) DSim

Example of C/C++ register access with name through UVM RAL

UVM + DPI-C reference model for PCIe Gen3 endpoint (transaction layer)

First Step in UVM

Small wrapper for SystemVerilog DPI-C header svdpi.h

AES-128 co-simulation between SystemVerilog, C DPI, and Python for hardware verification.

UVM testbench for AES-256 VHDL design running alongside C model tied over DPI using golden NIST and random vectors, with code & functional coverage collection

Basic APB-compatible module designed for use with Verilator, but should work with any DPI-C compatible simulator.

UVM-based verification environment for a 5-stage RV32I RISC-V pipeline using constrained-random testing, DPI-C golden reference modeling, assertions, scoreboarding, functional coverage, and 20-seed QuestaSim regression debugging.