Updated test generators to not use MTIME if undefined

Author: davidharrishmc

docs/ctp/src/rvmodel.adoc

@@ -40,8 +40,8 @@ The RVMODEL DUT-Specific Macros are given in <<t-rvmodel>>. The "Can Be Empty?"
 |RVMODEL_SET_SSW_INT(_R1, _R2)|Sets the Supervisor Software Interrupt `sip.SSIP` using a platform-specific interrupt controller, if supported. _R1 and _R2 are temporary registers that may be trashed by the macro.|If S-mode software interrupts are not tested.  | Machine or Supervisor
 |RVMODEL_CLR_SSW_INT(_R1, _R2)|Clears the Supervisor Software Interrupt `sip.SSIP` by using a platform-specific interrupt controller, as applicable. _R1 and _R2 are temporary registers that may be trashed by the macro.|If S-mode software interrupts are not tested.  | Machine or Supervisor
 |RVMODEL_ACCESS_FAULT_ADDRESS|The base physical address of a region of at least 128 bytes that causes an access fault when any part of the region is read or written. This is used to test exceptions.|Omit if DUT does not generate some/all access faults.| n/a
-|RVMODEL_MTIME_ADDRESS|The address of the memory-mapped `mtime` register, used for timer accesses and interrupts.|Omit if timer interrupts are not tested. | n/a
-|RVMODEL_MTIMECMP_ADDRESS|The address of the memory-mapped `mtimecmp` register, used for timer interrupts.| Omit if Machine timer interrupts are not tested. | n/a
+|RVMODEL_MTIME_ADDRESS|The address of the memory-mapped `mtime` register, used for timer accesses and interrupts.|Omit if machine timer interrupts are not tested. | n/a
+|RVMODEL_MTIMECMP_ADDRESS|The address of the memory-mapped `mtimecmp` register, used for timer interrupts.| Omit if machine timer interrupts are not tested. | n/a
 |RVMODEL_INTERRUPT_LATENCY|Expected latency (in cycles/NOPs) for interrupt trap processing. Ensures interrupt is received and can be processed before test continues.|Can be 0 if interrupt controller adds no delay. | n/a
 |RVMODEL_TIMER_INT_SOON_DELAY|The delay (in cycles) before a timer interrupt fires when using `set_mtimer_int_soon()`. Sets `mtimecmp = mtime + delay`. Should be long enough that the core can run a few instructions before the interrupt fires.| If Machine timer interrupts are not tested. | n/a
 |RVMODEL_DATA_SECTION|DUT-specific data that will be placed in a .data section. Used for memory-mapped regions like `tohost`/`fromhost`.  |Yes, if not needed by DUT. | n/a

generators/testgen/src/testgen/asm/interrupts.py

@@ -20,7 +20,8 @@ def set_mtimer_int(r_mtime: int, r_mtimecmp: int, r_temp: int, r_temp2: int) ->
         r_temp2: Second temp register number for RV32
     """
     return [
-        f"{INDENT}# Cause machine timer interrupt",
+        f"{INDENT}# Cause machine timer interrupt if supported",
+        "#ifdef RVMODEL_MTIME_ADDRESS",
         f"LA(x{r_mtime}, RVMODEL_MTIME_ADDRESS)",
         f"LA(x{r_mtimecmp}, RVMODEL_MTIMECMP_ADDRESS)",
         "#if __riscv_xlen == 64",
@@ -37,6 +38,7 @@ def set_mtimer_int(r_mtime: int, r_mtimecmp: int, r_temp: int, r_temp2: int) ->
         f"sw x{r_temp2}, 4(x{r_mtimecmp}) # Step 2: Write high word (no smaller than new)",
         f"sw x{r_temp}, 0(x{r_mtimecmp}) # Step 3: Write low word (new value)",
         "#endif",
+        "#endif",
     ]
 
 
@@ -72,7 +74,8 @@ def set_mtimer_int_soon(
         r_temp1, r_temp2, r_temp3, r_temp4: Temp registers for calculations
     """
     return [
-        f"{INDENT}# Cause machine timer interrupt soon",
+        f"{INDENT}# Cause machine timer interrupt soon if supported",
+        "#ifdef RVMODEL_MTIME_ADDRESS",
         f"LA(x{r_mtime}, RVMODEL_MTIME_ADDRESS)",
         f"LA(x{r_mtimecmp}, RVMODEL_MTIMECMP_ADDRESS)",
         "#if __riscv_xlen == 64",
@@ -99,6 +102,7 @@ def set_mtimer_int_soon(
         f"sw x{r_temp2}, 4(x{r_mtimecmp})",  # Write high word
         f"sw x{r_temp3}, 0(x{r_mtimecmp})",  # Write low word (final value)
         "#endif",
+        "#endif",
     ]
 
 
@@ -122,7 +126,7 @@ def set_stimer_int(r_mtime: int, r_temp: int, r_temp2: int, r_scratch: int) -> l
         f"BEQZ x{r_scratch}, 1f # If STCE=0, use non sstc method",
         "",
         f"{INDENT}# Sstc method: Write stimecmp",
-        f"LA(x{r_mtime}, RVMODEL_MTIME_ADDRESS)",
+        f"LA(x{r_mtime}, RVMODEL_MTIME_ADDRESS) # NOTE: This will need to be replaced by a SBI call because MTIME might not exist or be accessible",
         f"LREG x{r_temp}, 0(x{r_mtime})",
         f"csrw stimecmp, x{r_temp}",
         "nop",
@@ -188,7 +192,7 @@ def set_stimer_int_soon_sstc(r_mtime: int, r_temp1: int, r_temp2: int, r_temp3:
     """
     return [
         f"{INDENT}# Set supervisor timer interrupt to fire soon with Sstc extension",
-        f"LA(x{r_mtime}, RVMODEL_MTIME_ADDRESS)",
+        f"LA(x{r_mtime}, RVMODEL_MTIME_ADDRESS)  # NOTE: This will need to be replaced by a SBI call because MTIME might not exist or be accessible",
         "#if __riscv_xlen == 64",
         f"{INDENT}# Disable comparator first",
         f"LI(x{r_temp1}, -1)",

generators/testgen/src/testgen/priv/extensions/Sm.py

@@ -796,11 +796,12 @@ def _generate_mcsr_cntr_tests(test_data: TestData) -> list[str]:
     lines.append(
         comment_banner(
             coverpoint,
-            "Write mtime and read back time",
+            "Write mtime and read back time if supported",
         ),
     )
     lines.extend(
         [
+            "#ifdef RVMODEL_MTIME_ADDRESS",
             f"LI(x{r1}, 42)        # value to write to mtime",
             f"LA(x{r2}, RVMODEL_MTIME_ADDRESS)        # load address of mtime",
             f"SREG x{r1}, 0(x{r2})        # write mtime = 42 using memory-mapped I/O",
@@ -819,6 +820,7 @@ def _generate_mcsr_cntr_tests(test_data: TestData) -> list[str]:
             f"sub x{r2}, x{r2}, x{r1}          # difference should be zero",
             write_sigupd(r2, test_data),
             "#endif",
+            "#endif",
         ]
     )
 

tests/env/check_defines.h

@@ -46,12 +46,15 @@
 #endif
 
 ##### MTIME #####
-#ifndef RVMODEL_MTIME_ADDRESS
-  #error "RVMODEL_MTIME_ADDRESS not defined. Make sure to define it in rvmodel_macros.h."
-#endif
-
-#ifndef RVMODEL_MTIMECMP_ADDRESS
-  #error "RVMODEL_MTIMECMP_ADDRESS not defined. Make sure to define it in rvmodel_macros.h."
+# If RVMODEL_MTIME_ADDRESS is not defined, no machine timer interrupts are tested
+
+#ifdef RVMODEL_MTIME_ADDRESS
+  # If RVMODEL_MTIME_ADDRESS is defined, these other MTIME-related macros must also be defined
+  # because the tests will need them to cause timer interrupts and test timer functionality.
+  # If these macros are not defined, the tests will fail to assemble due to the checks below.
+  #ifndef RVMODEL_MTIMECMP_ADDRESS
+    #error "RVMODEL_MTIMECMP_ADDRESS not defined. Make sure to define it in rvmodel_macros.h."
+  #endif
 #endif
 
 ##### Interrupt Delays #####