Skip to content

Commit 14fcd7e

Browse files
davidharrishmcjordancarlin
davidharrishmc
and
jordancarlin
authored
ImperasDV for Phase 0 (#1106)
Run with `make imperasfpm` Passes all Phase0 tests except RV64 Zalrsc where sc.d following lr.w fails in ImperasFPM but passes in Sail. Sail lacks configuration to check that the two sizes match. This is the same issue seen in QEMU on the same test. Passes all RVA22 unpriv tests as well. Not working on Phase1 tests because of WARL mismatches, exception behaviors. Also improved reporting on coverage. --------- Co-authored-by: Jordan Carlin <jordanmcarlin@gmail.com>
1 parent 72fa7e5 commit 14fcd7e

41 files changed

Lines changed: 3123 additions & 88 deletions

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

‎Makefile‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,35 @@ qemu-rv64: CONFIG_FILES = config/qemu/qemu-rv64-max/test_config.yaml
9292
qemu-rv64: elfs
9393
./run_tests.py "$(QEMU_RV64_CMD)" $(WORKDIR)/qemu-rv64-max/elfs
9494

95+
##### ImperasFPM test targets #####
96+
.PHONY: imperasfpm imperasfpm-rv32 imperasfpm-rv64
97+
98+
# Add --trace before --program to see a trace of the executed instructions for debug
99+
IMPERASFPM_RV32_MAX_CMD := IMPERAS_TOOLS=config/imperasfpm/imperasfpm-rv32-max/imperas.ic iss.exe --verbose --program
100+
IMPERASFPM_RV64_MAX_CMD := IMPERAS_TOOLS=config/imperasfpm/imperasfpm-rv64-max/imperas.ic iss.exe --verbose --program
101+
IMPERASFPM_RVI20U32_CMD := IMPERAS_TOOLS=config/imperasfpm/imperasfpm-RVI20U32/imperas.ic iss.exe --verbose --program
102+
IMPERASFPM_RVI20U64_CMD := IMPERAS_TOOLS=config/imperasfpm/imperasfpm-RVI20U64/imperas.ic iss.exe --verbose --program
103+
104+
imperasfpm: CONFIG_FILES = config/imperasfpm/imperasfpm-rv32-max/test_config.yaml config/imperasfpm/imperasfpm-rv64-max/test_config.yaml config/imperasfpm/imperasfpm-RVI20U64/test_config.yaml config/imperasfpm/imperasfpm-RVI20U32/test_config.yaml
105+
imperasfpm: elfs
106+
@exit_code=0; \
107+
./run_tests.py "$(IMPERASFPM_RV64_MAX_CMD)" $(WORKDIR)/imperasfpm-rv64-max/elfs || exit_code=1; \
108+
./run_tests.py "$(IMPERASFPM_RV32_MAX_CMD)" $(WORKDIR)/imperasfpm-rv32-max/elfs || exit_code=1; \
109+
./run_tests.py "$(IMPERASFPM_RVI20U64_CMD)" $(WORKDIR)/imperasfpm-RVI20U64/elfs || exit_code=1; \
110+
./run_tests.py "$(IMPERASFPM_RVI20U32_CMD)" $(WORKDIR)/imperasfpm-RVI20U32/elfs || exit_code=1; \
111+
exit $$exit_code
112+
113+
# Add --verbose to run_tests.py arguments to see the simulator commands
114+
imperasfpm-rv32: CONFIG_FILES = config/imperasfpm/imperasfpm-rv32-max/test_config.yaml
115+
imperasfpm-rv32: elfs
116+
./run_tests.py "$(IMPERASFPM_RV32_MAX_CMD)" $(WORKDIR)/imperasfpm-rv32-max/elfs
117+
118+
imperasfpm-rv64: CONFIG_FILES = config/imperasfpm/imperasfpm-rv64-max/test_config.yaml
119+
imperasfpm-rv64: elfs
120+
./run_tests.py "$(IMPERASFPM_RV64_MAX_CMD)" $(WORKDIR)/imperasfpm-rv64-max/elfs
121+
122+
123+
95124

96125
###### Test compilation targets ######
97126
.PHONY: elfs

‎config/imperasfpm/imperasfpm-RVI20U32/imperas.ic‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
# imperas.ic
2+
# Initialization file for rv32gc ImperasDV lock step simulation
3+
# David_Harris@hmc.edu 15 August 2024
4+
# jcarlin@hmc.edu 19 March 2025
5+
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
6+
7+
# Base configuration
8+
--processorvendor riscv.ovpworld.org
9+
--processorname riscv
10+
--variant RVI20U32
11+
# defines printing via write to 0x10010000 and termination at symbol _test_exit
12+
--extlib iss/cpu0/cc=riscv.ovpworld.org/intercept/customControl/1.0
13+
14+
# Misaligned access (Zicclsm)
15+
--override cpu*/unaligned=T

‎config/imperasfpm/imperasfpm-RVI20U32/imperasfpm-RVI20U32.yaml‎

Lines changed: 157 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,157 @@
1+
# yaml-language-server: $schema=../../../external/riscv-unified-db/spec/schemas/config_schema.json
2+
---
3+
$schema: config_schema.json#
4+
kind: architecture configuration
5+
type: fully configured
6+
name: imperasfpm-RVI20U32
7+
description: RVI20U32 with all optional extensions
8+
implemented_extensions:
9+
- { name: I, version: "= 2.1" }
10+
- { name: M, version: "= 2.0" }
11+
- { name: A, version: "= 2.1.0" }
12+
- { name: F, version: "= 2.2.0" }
13+
- { name: D, version: "= 2.2.0" }
14+
- { name: C, version: "= 2.0" }
15+
- { name: Zicntr, version: "= 2.0" }
16+
- { name: Zihpm, version: "= 2.0" }
17+
# Smhpm is a fake extension for UDB purposes, due to be deleted soon. Remove when possible. DH 3/22/26
18+
- { name: Smhpm, version: "= 1.12" }
19+
- { name: Zicsr, version: "= 2.0" }
20+
- { name: Zifencei, version: "= 2.0.0" }
21+
- { name: Zaamo, version: "= 1.0.0" }
22+
- { name: Zalrsc, version: "= 1.0.0" }
23+
- { name: Zca, version: "= 1.0.0" }
24+
- { name: Zcf, version: "= 1.0.0" }
25+
- { name: Zcd, version: "= 1.0.0" }
26+
- { name: Sm, version: "= 1.12.0" }
27+
28+
params:
29+
# A params
30+
MISALIGNED_AMO: false
31+
LRSC_RESERVATION_STRATEGY: "reserve exactly enough to cover the access" # XLEN size reservation
32+
LRSC_FAIL_ON_VA_SYNONYM: false
33+
LRSC_MISALIGNED_BEHAVIOR: "always raise access fault"
34+
LRSC_FAIL_ON_NON_EXACT_LRSC: false
35+
MUTABLE_MISA_A: false
36+
# M params
37+
MUTABLE_MISA_M: false
38+
# F params
39+
MUTABLE_MISA_F: false
40+
HW_MSTATUS_FS_DIRTY_UPDATE: precise
41+
MSTATUS_FS_LEGAL_VALUES: [0, 1, 2, 3]
42+
# D params
43+
MUTABLE_MISA_D: false
44+
# C params
45+
MUTABLE_MISA_C: false
46+
# Zicntr params
47+
TIME_CSR_IMPLEMENTED: true
48+
# Sm params
49+
MXLEN: 32
50+
PRECISE_SYNCHRONOUS_EXCEPTIONS: true
51+
TRAP_ON_ECALL_FROM_M: true
52+
TRAP_ON_EBREAK: true
53+
MARCHID_IMPLEMENTED: true
54+
ARCH_ID_VALUE: 0x1
55+
MIMPID_IMPLEMENTED: true
56+
IMP_ID_VALUE: 0x0
57+
VENDOR_ID_BANK: 0x0
58+
VENDOR_ID_OFFSET: 0x0
59+
MISALIGNED_LDST: true
60+
MISALIGNED_LDST_EXCEPTION_PRIORITY: low
61+
MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE: 4096
62+
MISALIGNED_SPLIT_STRATEGY: sequential_bytes
63+
TRAP_ON_ILLEGAL_WLRL: false
64+
TRAP_ON_UNIMPLEMENTED_INSTRUCTION: true
65+
TRAP_ON_RESERVED_INSTRUCTION: true
66+
TRAP_ON_UNIMPLEMENTED_CSR: true
67+
REPORT_VA_IN_MTVAL_ON_BREAKPOINT: true
68+
REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED: true
69+
REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED: true
70+
REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED: true
71+
REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT: true
72+
REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT: true
73+
REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT: true
74+
REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION: true
75+
MTVAL_WIDTH: 32
76+
CONFIG_PTR_ADDRESS: 0
77+
PMA_GRANULARITY: 3
78+
PHYS_ADDR_WIDTH: 32
79+
M_MODE_ENDIANNESS: little
80+
MISA_CSR_IMPLEMENTED: true
81+
MTVEC_ACCESS: rw
82+
MTVEC_MODES: [0, 1]
83+
MTVEC_BASE_ALIGNMENT_DIRECT: 4
84+
MTVEC_BASE_ALIGNMENT_VECTORED: 4
85+
MTVEC_ILLEGAL_WRITE_BEHAVIOR: retain
86+
# Smhpm params
87+
HPM_COUNTER_EN:
88+
[
89+
false,
90+
false,
91+
false,
92+
true,
93+
true,
94+
true,
95+
true,
96+
true,
97+
true,
98+
true,
99+
true,
100+
true,
101+
true,
102+
true,
103+
true,
104+
true,
105+
true,
106+
true,
107+
true,
108+
true,
109+
true,
110+
true,
111+
true,
112+
true,
113+
true,
114+
true,
115+
true,
116+
true,
117+
true,
118+
true,
119+
true,
120+
true,
121+
]
122+
HPM_EVENTS: [0]
123+
COUNTINHIBIT_EN:
124+
[
125+
true,
126+
false,
127+
true,
128+
true,
129+
true,
130+
true,
131+
true,
132+
true,
133+
true,
134+
true,
135+
true,
136+
true,
137+
true,
138+
true,
139+
true,
140+
true,
141+
true,
142+
true,
143+
true,
144+
true,
145+
true,
146+
true,
147+
true,
148+
true,
149+
true,
150+
true,
151+
true,
152+
true,
153+
true,
154+
true,
155+
true,
156+
true,
157+
]

‎config/imperasfpm/imperasfpm-RVI20U32/link.ld‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
../imperasfpm-rv64-max/link.ld

‎config/imperasfpm/imperasfpm-RVI20U32/rvmodel_macros.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
../imperasfpm-rv64-max/rvmodel_macros.h

‎config/imperasfpm/imperasfpm-RVI20U32/rvtest_config.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
../../sail/sail-RVI20U32/rvtest_config.h

‎config/imperasfpm/imperasfpm-RVI20U32/rvtest_config.svh‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
../../sail/sail-RVI20U32/rvtest_config.svh

‎config/imperasfpm/imperasfpm-RVI20U32/sail.json‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
../../sail/sail-RVI20U32/sail.json

‎config/imperasfpm/imperasfpm-RVI20U32/test_config.yaml‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,7 @@
1+
name: imperasfpm-RVI20U32
2+
compiler_exe: riscv64-unknown-elf-gcc # executable name on $PATH or full path to executable
3+
objdump_exe: riscv64-unknown-elf-objdump # executable name on $PATH or full path to executable, optional
4+
ref_model_exe: sail_riscv_sim # executable name on $PATH or full path to executable
5+
udb_config: imperasfpm-RVI20U32.yaml
6+
linker_script: link.ld
7+
dut_include_dir: . # Directory containing DUT specific rvmodel_macros.h header

‎config/imperasfpm/imperasfpm-RVI20U64/imperas.ic‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
# imperas.ic
2+
# Initialization file for rv64gc ImperasDV lock step simulation
3+
# David_Harris@hmc.edu 15 August 2024
4+
# jcarlin@hmc.edu 19 March 2025
5+
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
6+
7+
# Base configuration
8+
--processorvendor riscv.ovpworld.org
9+
--processorname riscv
10+
--variant RVI20U64
11+
# defines printing via write to 0x10010000 and termination at symbol _test_exit
12+
--extlib iss/cpu0/cc=riscv.ovpworld.org/intercept/customControl/1.0
13+
14+
# Misaligned access (Zicclsm) is supported
15+
--override cpu*/unaligned=T

0 commit comments

Comments
 (0)