Delay interrupt acknowledgement, add HALT instruction

Author: mnaberez

k0emu/processor.py

@@ -18,6 +18,7 @@ def __init__(self, bus=None):
         self._init_opcode_map_prefix_0x71()
         self._total_cycles = 0
         self._inst_cycles = 0
+        self._interrupt_delayed = False
         self.pc = 0
 
     def reset(self):
@@ -27,18 +28,18 @@ def reset(self):
         self._inst_cycles = 0
 
     def step(self):
+        # fetch and execute the instruction
         self._inst_cycles = 0
         opcode = self._consume_byte()
         handler = self._opcode_map_unprefixed.get(opcode, self._opcode_not_implemented)
         handler(opcode)
         self._total_cycles += self._inst_cycles
 
+        # clock peripherals by number of cycles instruction consumed
         self.bus.tick(self._inst_cycles)
 
-        if self.read_psw() & Flags.IE:  # enabled
-            pending = self.bus.pending_interrupt
-            if pending is not None:
-                self._service_interrupt(pending)
+        # service interrupt
+        self._service_interrupt()
 
     @property
     def total_cycles(self):
@@ -64,20 +65,31 @@ def _bus_write(self, address, value):
             self._inst_cycles += 1
         self.bus.write(address, value)
 
-    def _service_interrupt(self, pending):
-        if (self.read_psw() & Flags.ISP) and not pending.high_priority:
-            return  # low-priority blocked by high-priority ISR
+    def _service_interrupt(self):
+        # according to the programming manual, after EI or RETI, the 
+        # one instruction is executed before acknowledging any interrupt.
+        if self._interrupt_delayed:
+            self._interrupt_delayed = False
+            return
 
-        self.bus.acknowledge_interrupt(pending)
+        psw = self.read_psw()
 
-        # Push PSW and PC, clear IE, set ISP if high priority
-        self._push(self.read_psw())
-        psw = self.read_psw() & ~Flags.IE
+        if not (psw & Flags.IE):
+            return  # interrupts must be enabled
+        if psw & Flags.ISP:
+            return  # must not already be in a high priority interrupt
+
+        pending = self.bus.pending_interrupt
+        if pending is None:
+            return
+
+        self.bus.acknowledge_interrupt(pending)
+        self._push(psw)
+        psw &= ~Flags.IE
         if pending.high_priority:
             psw |= Flags.ISP
         self.write_psw(psw)
         self._push_word(self.pc)
-
         self.pc = self.read_memory_word(pending.vector_address)
 
     def _init_opcode_map_unprefixed(self):
@@ -455,9 +467,11 @@ def _init_opcode_map_prefix_0x71(self):
         # xor1 cy,0fe20h.0            ;71 07 20       saddr
         for opcode2 in (0x07, 0x17, 0x27, 0x37, 0x47, 0x57, 0x67, 0x77):
             D[opcode2] = self._opcode_0x71_0x07_to_0x77_xor1
+        # halt                        ;71 10
+        D[0x10] = self._opcode_0x71_0x10_halt
+
         self._opcode_map_prefix_0x71 = D
 
-    # not implemented
     def _opcode_not_implemented(self, opcode):
         raise NotImplementedError()
 
@@ -1705,15 +1719,6 @@ def _opcode_0x61_0x20_to_0x27_addc(self, opcode2):
         self.write_gp_reg(reg, result)
         self._inst_cycles += 2
 
-    # set1 [hl].0                 ;71 82
-    def _opcode_0x71_0x82_to_0xf2_set1(self, opcode2):
-        bit = _bit(opcode2)
-        address = self.read_gp_regpair(RegisterPairs.HL)
-        value = self._bus_read(address)
-        result = self._operation_set1(value, bit)
-        self._bus_write(address, result)
-        self._inst_cycles += 2
-
     # clr1 0fffeh.0               ;71 0b fe       sfr
     def _opcode_0x71_0x0b_to_0x7b_clr1(self, opcode2):
         bit = _bit(opcode2)
@@ -1732,6 +1737,21 @@ def _opcode_0x71_0x0a_to_0x7a_set1(self, opcode2):
         self._bus_write(address, result)
         self._inst_cycles += 1
 
+    # halt                            ;71 10
+    def _opcode_0x71_0x10_halt(self, opcode):
+        while self.bus.pending_interrupt is None:
+            self._total_cycles += 1
+            self.bus.tick(1)
+
+    # set1 [hl].0                 ;71 82
+    def _opcode_0x71_0x82_to_0xf2_set1(self, opcode2):
+        bit = _bit(opcode2)
+        address = self.read_gp_regpair(RegisterPairs.HL)
+        value = self._bus_read(address)
+        result = self._operation_set1(value, bit)
+        self._bus_write(address, result)
+        self._inst_cycles += 2
+
     # clr1 [hl].0                 ;71 83
     def _opcode2_0x71_0x83_to_0xf3_clr1(self, opcode2):
         bit = _bit(opcode2)
@@ -2124,6 +2144,9 @@ def _opcode_0x0a_to_0x7a_set1(self, opcode):
         value = self._bus_read(address)
         result = self._operation_set1(value, bit)
         self._bus_write(address, result)
+        # after EI (set1 PSW.7), interrupt acknowledge must be delayed
+        if (address == self.PSW_ADDRESS) and (bit == 7):
+            self._interrupt_delayed = True
 
     # clr1 0fe20h.0               ;0b 20          saddr
     # clr1 psw.0                  ;0b 1e
@@ -2144,6 +2167,7 @@ def _opcode_0xaf(self, opcode):
     def _opcode_0x8f(self, opcode):
         self.pc = self._pop_word()
         self.write_psw(self._pop())
+        self._interrupt_delayed = True
         self._inst_cycles += 2
 
     # retb                        ;9f

k0emu/tests/test_processor_interrupts.py

@@ -1,5 +1,5 @@
 import unittest
-from k0emu.devices import MemoryDevice, InterruptControllerDevice
+from k0emu.devices import MemoryDevice, InterruptControllerDevice, WatchTimerDevice
 from k0emu.processor import Processor, Flags
 
 
@@ -66,7 +66,7 @@ def test_low_priority_blocked_when_isp_set(self):
         proc.step()
         self.assertEqual(proc.pc, 1)  # blocked, not vectored
 
-    def test_high_priority_not_blocked_when_isp_set(self):
+    def test_high_priority_blocked_when_isp_set(self):
         proc, mem, intc, dev = _make_processor()
         mem.write(0, 0x00)  # NOP
         mem.write(0x0006, 0x00)
@@ -77,7 +77,7 @@ def test_high_priority_not_blocked_when_isp_set(self):
         proc.write_psw(Flags.IE | Flags.ISP)
         proc.pc = 0
         proc.step()
-        self.assertEqual(proc.pc, 0x1000)
+        self.assertEqual(proc.pc, 1)  # blocked, not vectored
 
 
 class InterruptEntryTests(unittest.TestCase):
@@ -255,3 +255,110 @@ def test_inttm52_vectors_to_003c(self):
         proc.pc = 0
         proc.step()
         self.assertEqual(proc.pc, 0x2000)
+
+
+def _make_processor_with_timer():
+    """Create a processor with memory, interrupt controller, and watch timer."""
+    proc = Processor()
+    mem = MemoryDevice("test_memory", size=0xFF41)
+    proc.bus.add_device(mem, (0x0000, 0xFF40))
+    intc = InterruptControllerDevice("intc")
+    proc.bus.add_device(intc, (0xFFE0, 0xFFEB))
+    proc.bus.set_interrupt_controller(intc)
+    wt = WatchTimerDevice("watch_timer")
+    proc.bus.add_device(wt, (0xFF41, 0xFF41))
+    intc.connect(wt, wt.INT_PRESCALER, intc.INTWTNI0)
+    return proc, mem, intc, wt
+
+
+class HaltTests(unittest.TestCase):
+    """Tests for the HALT instruction (0x71 0x10)."""
+
+    def test_halt_wakes_on_pending_interrupt(self):
+        proc, mem, intc, wt = _make_processor_with_timer()
+        # HALT at address 0
+        mem.write(0, 0x71)
+        mem.write(1, 0x10)
+        # ISR at vector 0x0024 (INTWTNI0) points to 0x2000
+        mem.write(0x0024, 0x00)
+        mem.write(0x0025, 0x20)
+        # Enable watch timer: WTNM00=1, n=0, fw=128 -> interval=2048
+        wt.write(0, 0x01)
+        # Unmask INTWTNI0
+        intc.write(intc.MK1L, intc.read(intc.MK1L) & 0xFE)
+        proc.write_psw(Flags.IE)
+        proc.write_sp(0xFE00)
+        proc.pc = 0
+        proc.step()
+        # HALT should have waited for the timer, then serviced the interrupt
+        self.assertEqual(proc.pc, 0x2000)
+
+    def test_halt_advances_cycles(self):
+        proc, mem, intc, wt = _make_processor_with_timer()
+        mem.write(0, 0x71)
+        mem.write(1, 0x10)
+        mem.write(0x0024, 0x00)
+        mem.write(0x0025, 0x20)
+        wt.write(0, 0x01)  # interval=2048
+        intc.write(intc.MK1L, intc.read(intc.MK1L) & 0xFE)
+        proc.write_psw(Flags.IE)
+        proc.write_sp(0xFE00)
+        proc.pc = 0
+        cycles_before = proc.total_cycles
+        proc.step()
+        # Should have waited ~2048 cycles for the timer
+        elapsed = proc.total_cycles - cycles_before
+        self.assertGreaterEqual(elapsed, 2048)
+
+    def test_halt_does_not_double_tick(self):
+        proc, mem, intc, wt = _make_processor_with_timer()
+        mem.write(0, 0x71)
+        mem.write(1, 0x10)
+        mem.write(0x0024, 0x00)
+        mem.write(0x0025, 0x20)
+        wt.write(0, 0x01)  # interval=2048
+        intc.write(intc.MK1L, intc.read(intc.MK1L) & 0xFE)
+        proc.write_psw(Flags.IE)
+        proc.write_sp(0xFE00)
+        proc.pc = 0
+        proc.step()
+        # The timer should have fired exactly once (no double-ticking).
+        # After firing, the prescaler counter resets to a small remainder.
+        self.assertLess(wt._prescaler_counter, 100)
+
+    def test_halt_with_interrupt_already_pending(self):
+        proc, mem, intc, wt = _make_processor_with_timer()
+        mem.write(0, 0x71)
+        mem.write(1, 0x10)
+        mem.write(0x0024, 0x00)
+        mem.write(0x0025, 0x20)
+        # Set IF flag before HALT
+        intc.write(intc.IF1L, 0x01)  # INTWTNI0 already pending
+        intc.write(intc.MK1L, intc.read(intc.MK1L) & 0xFE)
+        proc.write_psw(Flags.IE)
+        proc.write_sp(0xFE00)
+        proc.pc = 0
+        cycles_before = proc.total_cycles
+        proc.step()
+        # Should wake almost immediately
+        self.assertEqual(proc.pc, 0x2000)
+        elapsed = proc.total_cycles - cycles_before
+        # Only the HALT fetch cycles + 1 tick to detect the pending interrupt
+        self.assertLess(elapsed, 20)
+
+    def test_halt_resumes_at_next_instruction_when_ie_disabled(self):
+        proc, mem, intc, wt = _make_processor_with_timer()
+        # HALT at address 0, NOP at address 2
+        mem.write(0, 0x71)
+        mem.write(1, 0x10)
+        mem.write(2, 0x00)  # NOP
+        # Set IF flag but IE=0 so interrupt won't be serviced
+        intc.write(intc.IF1L, 0x01)
+        intc.write(intc.MK1L, intc.read(intc.MK1L) & 0xFE)
+        proc.write_psw(0)  # IE=0
+        proc.write_sp(0xFE00)
+        proc.pc = 0
+        proc.step()
+        # HALT wakes on the unmasked interrupt request but since IE=0,
+        # it executes the next instruction instead of vectoring
+        self.assertEqual(proc.pc, 2)