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sha256_processor_waveform.vcd
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7182 lines (7180 loc) · 127 KB
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$version Generated by VerilatedVcd $end
$timescale 1ps $end
$scope module TOP $end
$var wire 1 (! ext_clk $end
$var wire 1 )! test_complete $end
$var wire 1 *! test_passed $end
$scope module sha256_processor_tb $end
$var wire 1 (! ext_clk $end
$var wire 1 )! test_complete $end
$var wire 1 *! test_passed $end
$var wire 1 (! clk $end
$var wire 1 # rst $end
$var wire 1 $ start $end
$var wire 8 % data_in [7:0] $end
$var wire 1 & data_valid $end
$var wire 1 ' data_last $end
$var wire 256 ) hash_out [255:0] $end
$var wire 1 1 done $end
$var wire 32 +! FILE_SIZE [31:0] $end
$var wire 32 ( i [31:0] $end
$var wire 256 ,! EXPECTED_HASH [255:0] $end
$scope module uut $end
$var wire 1 (! clk $end
$var wire 1 # rst $end
$var wire 1 $ start $end
$var wire 8 % data_in [7:0] $end
$var wire 1 & data_valid $end
$var wire 1 ' data_last $end
$var wire 256 ) hash_out [255:0] $end
$var wire 1 1 done $end
$var wire 32 +! BLOCK_SIZE [31:0] $end
$var wire 512 2 block_buffer [511:0] $end
$var wire 6 B byte_index [5:0] $end
$var wire 1 C block_ready $end
$var wire 3 D state [2:0] $end
$var wire 32 4! IDLE [31:0] $end
$var wire 32 5! LOAD [31:0] $end
$var wire 32 6! PAD [31:0] $end
$var wire 32 7! HASH [31:0] $end
$var wire 32 8! DONE [31:0] $end
$var wire 256 E core_hash_out [255:0] $end
$var wire 1 M core_ready $end
$var wire 1 N core_start $end
$var wire 512 O core_block [511:0] $end
$var wire 256 _ core_hash_init [255:0] $end
$var wire 1 g core_use_init $end
$var wire 1 h core_busy $end
$var wire 1 i core_ready_prev $end
$var wire 256 ) hash_state [255:0] $end
$var wire 64 j total_bits [63:0] $end
$var wire 1 l seen_last $end
$var wire 1 m need_length_block $end
$var wire 6 n pad_index [5:0] $end
$var wire 32 o i [31:0] $end
$scope module sha_core $end
$var wire 1 (! clk $end
$var wire 1 # rst $end
$var wire 1 N start $end
$var wire 512 O block_in [511:0] $end
$var wire 256 _ hash_init [255:0] $end
$var wire 1 g use_init $end
$var wire 256 E hash_out [255:0] $end
$var wire 1 M ready $end
$var wire 32 9! H0_INIT [31:0] $end
$var wire 32 :! H1_INIT [31:0] $end
$var wire 32 ;! H2_INIT [31:0] $end
$var wire 32 <! H3_INIT [31:0] $end
$var wire 32 =! H4_INIT [31:0] $end
$var wire 32 >! H5_INIT [31:0] $end
$var wire 32 ?! H6_INIT [31:0] $end
$var wire 32 @! H7_INIT [31:0] $end
$var wire 32 p a [31:0] $end
$var wire 32 q b [31:0] $end
$var wire 32 r c [31:0] $end
$var wire 32 s d [31:0] $end
$var wire 32 t e [31:0] $end
$var wire 32 u f [31:0] $end
$var wire 32 v g [31:0] $end
$var wire 32 w h [31:0] $end
$var wire 32 x h0 [31:0] $end
$var wire 32 y h1 [31:0] $end
$var wire 32 z h2 [31:0] $end
$var wire 32 { h3 [31:0] $end
$var wire 32 | h4 [31:0] $end
$var wire 32 } h5 [31:0] $end
$var wire 32 ~ h6 [31:0] $end
$var wire 32 !! h7 [31:0] $end
$var wire 7 "! t [6:0] $end
$var wire 7 #! msg_idx [6:0] $end
$var wire 2 $! state [1:0] $end
$var wire 2 A! IDLE [1:0] $end
$var wire 2 B! PREP [1:0] $end
$var wire 2 C! COMP [1:0] $end
$var wire 2 D! DONE [1:0] $end
$var wire 32 %! T1 [31:0] $end
$var wire 32 &! T2 [31:0] $end
$var wire 32 '! i [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
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