This is work area for the CologneChip PHY PIPE developers.
- GateMate PIPE repo with DLL testbench ✔
- GateMate datasheet
- CologneChip PHY/PIPE Overview
- Unified PIPE Spec, Sept.2025, v7.1
- Optimizing PCIE PIPE Power Management
- TUSB1310A USB SuperSpeed PHY with PIPE
- Mithro on SerDes
- Yumewatari (whitequark) PHY segments with rudimentary LTSSM
See block diagram.
Hai:
"... our PIPE interface does not contain any functionality of the so called "MAC layer" which handles the training sequences, OSs and LTSSM..."
Simon
The LTSSM, I'd suggest, just needs to be the linear power up sequence from Detect.Quiet to L0 (Link UP) for first functionality (as per the table on page 14 of the PCIe Primer). Not part of the pcievhost proper, but the model comes with some demonstration code to implement the LTSSM to this spec., so we have a means to test this first implementation.
Async RefClock?
Does GateMate PHY support
Async RefClock?
That's when your 100MHz reference clock source comes from a different oscillator that the oscillator used by the Root Complex. They are both nominally 100MHz, but they are still different.
Hai: Simon has provided x1 PIPE model. All I had to do was to modify the C++ model of the RC for different feature tests and setup my MAC layer design as the EP. https://github.com/colognechip/gatemate-pipe/tree/dll_test/sim