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vmx.c
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2934 lines (2473 loc) · 76.6 KB
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/*
* SPDX-License-Identifier: GPL-2.0 OR MIT
* Copyright (c) 2026 Ant Group Corporation.
*
* vmx.c - The Intel VT-x driver for SlimVM
*
* This file is derived from Linux KVM VT-x support.
*
* This modified version is simpler because it avoids the following
* features that are not requirements for SlimVM:
* * Real-mode emulation
* * Nested VT-x support
* * I/O hardware emulation
* * Any of the more esoteric X86 features and registers
* * KVM-specific functionality
*
* In essence we provide only the minimum functionality needed to run
* a process in vmx non-root mode rather than the full hardware emulation
* needed to support an entire OS.
*
* This driver is a research prototype and as such has the following
* limitations:
*
* 1. Backward compatibility is currently a non-goal, and only recent
* full-featured (EPT, PCID, VPID, etc.) Intel hardware is supported
* by this driver.
*
* 2. SlimVM requires exclusive access to VT-x, so it is conflicted with
* KVM and other HV solutions.
*
* 3. Hotplugged physical CPUs are unsupported.
*/
#include <asm/virtext.h>
#include <linux/context_tracking.h>
#include <asm/virtext.h>
#include <asm/traps.h>
#include <asm/fpu/xcr.h>
#include <asm/syscall.h>
#include "vmx.h"
#include "compat.h"
#include "exception.h"
#include "seccomp.h"
/* Refer to arch/x86/include/asm/msr-index.h */
#undef MSR_IA32_FEATURE_CONTROL
#undef FEATURE_CONTROL_LOCKED
#undef FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
#undef FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
#define MSR_IA32_FEATURE_CONTROL 0x0000003a
#define FEATURE_CONTROL_LOCKED BIT(0)
#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX BIT(1)
#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX BIT(2)
static atomic_t vmx_enable_failed;
static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
static DEFINE_SPINLOCK(vmx_vpid_lock);
static struct vmcs_config vmcs_config;
static bool has_fsgsbase, has_pcid, has_osxsave, has_xsave;
u64 __read_mostly host_xcr0;
static unsigned long *msr_bitmap;
static __read_mostly struct preempt_ops slimvm_preempt_ops;
#define STACK_DEPTH 12
static sys_call_ptr_t slimvm_syscall_table[NR_syscalls] __cacheline_aligned;
static DEFINE_PER_CPU(struct vmcs *, vmxarea);
DEFINE_PER_CPU(struct desc_ptr, host_gdt);
DEFINE_PER_CPU(struct vmx_vcpu *, local_vcpu);
static DEFINE_PER_CPU(struct vmx_vcpu *, vmx_current_vcpu);
static DEFINE_PER_CPU(int, vmx_enabled);
struct vmx_capability vmx_capability;
#define VMX_SEGMENT_FIELD(seg) \
[VCPU_SREG_##seg] = { \
.selector = GUEST_##seg##_SELECTOR, \
.base = GUEST_##seg##_BASE, \
.limit = GUEST_##seg##_LIMIT, \
.ar_bytes = GUEST_##seg##_AR_BYTES, \
}
static const struct vmx_segment_field {
unsigned selector;
unsigned base;
unsigned limit;
unsigned ar_bytes;
} vmx_segment_fields[] = {
VMX_SEGMENT_FIELD(ES),
VMX_SEGMENT_FIELD(CS),
VMX_SEGMENT_FIELD(SS),
VMX_SEGMENT_FIELD(DS),
VMX_SEGMENT_FIELD(FS),
VMX_SEGMENT_FIELD(GS),
VMX_SEGMENT_FIELD(TR),
VMX_SEGMENT_FIELD(LDTR),
};
static const u32 vmx_msr_index[] = {
#ifdef CONFIG_X86_64
MSR_SYSCALL_MASK, MSR_LSTAR, MSR_KERNEL_GS_BASE,
#endif
MSR_EFER, MSR_STAR, MSR_MISC_FEATURES_ENABLES,
};
typedef long (*do_fork_hack) (struct kernel_clone_args *args);
typedef void (*do_exit_hack) (long);
typedef void (*do_group_exit_hack) (int);
static do_fork_hack __slimvm_do_fork;
static do_exit_hack __slimvm_do_exit;
static do_group_exit_hack __slimvm_do_group_exit;
/*
* tracehook_notify_resume defined in linux/tracehook.h is a static inline function,
* task_work_run is called in it, and task_work_run is not exported, so we
* can not directly call tracehook_notify_resume in linux/tracehook.h, but we can
* implement our slimvm_tracehook_notify_resume, and directly call the address of
* task_work_run in it.
*/
typedef void (*task_work_run_hack) (void);
typedef void (*mem_cgroup_handle_over_high_hack) (void);
static task_work_run_hack __slimvm_task_work_run;
static mem_cgroup_handle_over_high_hack __slimvm_mem_cgroup_handle_over_high;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0)
static __always_inline void guest_enter_irqoff(void)
{
instrumentation_begin();
vtime_account_guest_enter();
instrumentation_end();
if (!context_tracking_guest_enter()) {
instrumentation_begin();
rcu_virt_note_context_switch(smp_processor_id());
instrumentation_end();
}
}
static __always_inline void guest_exit_irqoff(void)
{
context_tracking_guest_exit();
instrumentation_begin();
/* Flush the guest cputime we spent on the guest */
vtime_account_guest_exit();
instrumentation_end();
}
#endif
/**
* copy from tracehook_notify_resume defined in linux/tracehook.h
* slimvm_tracehook_notify_resume - report when about to return to guest mode
* @regs: guest-mode registers of @current task
*
* This is called when %TIF_NOTIFY_RESUME has been set. Now we are
* about to return to guest mode, and the guest state in @regs can be
* inspected or adjusted. The caller in arch code has cleared
* %TIF_NOTIFY_RESUME before the call. If the flag gets set again
* asynchronously, this will be called again before we return to
* guest mode.
*
* Called without locks.
*/
static inline void slimvm_tracehook_notify_resume(void)
{
/*
* The caller just cleared TIF_NOTIFY_RESUME. This barrier
* pairs with task_work_add()->set_notify_resume() after
* hlist_add_head(task->task_works);
*/
smp_mb__after_atomic();
if (unlikely(current->task_works))
__slimvm_task_work_run();
__slimvm_mem_cgroup_handle_over_high();
}
static int enter_guestmode_loop(struct vmx_vcpu *vcpu, u32 cached_flags)
{
while (true) {
local_irq_enable();
if (cached_flags & _TIF_NEED_RESCHED)
schedule();
if (cached_flags & _TIF_NOTIFY_RESUME) {
clear_thread_flag(TIF_NOTIFY_RESUME);
slimvm_tracehook_notify_resume();
}
if (cached_flags & _TIF_SIGPENDING) {
if (__fatal_signal_pending(current)) {
local_irq_disable();
return -1;
}
if (slimvm_signal_handler(vcpu)) {
local_irq_disable();
return -1;
}
}
local_irq_disable();
cached_flags = READ_ONCE(current_thread_info()->flags);
if (!(cached_flags & ENTER_UESTMODE_FLAGS))
break;
}
return 0;
}
static int prepare_enter_guestmode(struct vmx_vcpu *vcpu)
{
struct thread_info *ti = current_thread_info();
u32 cached_flags;
int r = 0;
if (vcpu->shutdown || vcpu->instance->shutdown)
return -1;
/*
* In order to return to guest mode, we need to be with none of
* _TIF_SIGPENDING, _TIF_NOTIFY_RESUME, or _TIF_NEED_RESCHED set.
* Several of these flags can be set at any time on preemptable
* kernels if we have IRQs on, so we need to loop. Disabling
* preemption wouldn't help: doing the work to clear some of
* the flags can sleep.
*/
local_irq_disable();
cached_flags = READ_ONCE(ti->flags);
if (unlikely(cached_flags & ENTER_UESTMODE_FLAGS))
r = enter_guestmode_loop(vcpu, cached_flags);
local_irq_enable();
return r;
}
#define NR_SHARED_MSRS ARRAY_SIZE(vmx_msr_index)
#define NR_MSRS (NR_SHARED_MSRS + \
1 /* MSR_PLATFORM_INFO */ + \
1 /* PADDING */)
inline bool cpu_has_secondary_exec_ctrls(void)
{
return vmcs_config.cpu_based_exec_ctrl &
CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
}
inline bool cpu_has_vmx_invvpid_single(void)
{
return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
}
inline bool cpu_has_vmx_invvpid_global(void)
{
return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
}
inline bool cpu_has_vmx_invept_context(void)
{
return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
}
inline bool cpu_has_vmx_invept_global(void)
{
return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
}
inline bool cpu_has_vmx_ept_ad_bits(void)
{
return vmx_capability.ept & VMX_EPT_AD_BIT;
}
static inline void __vmxon(u64 addr)
{
asm volatile(ASM_VMX_VMXON_RAX
: : "a"(&addr), "m"(addr)
: "memory", "cc");
}
static inline void __vmxoff(void)
{
asm volatile(ASM_VMX_VMXOFF : : : "cc");
}
static inline void __invvpid(int ext, u16 vpid, gva_t gva)
{
struct {
u64 vpid : 16;
u64 rsvd : 48;
u64 gva;
} operand = {vpid, 0, gva};
asm volatile(ASM_VMX_INVVPID
/* CF==1 or ZF==1 --> rc = -1 */
"; ja 1f ; ud2 ; 1:"
: : "a"(&operand), "c"(ext) : "cc", "memory");
}
static inline void __invept(int ext, u64 eptp, gpa_t gpa)
{
struct {
u64 eptp, gpa;
} operand = {eptp, gpa};
asm volatile (ASM_VMX_INVEPT
/* CF==1 or ZF==1 --> rc = -1 */
"; ja 1f ; ud2 ; 1:\n"
: : "a" (&operand), "c" (ext) : "cc", "memory");
}
static inline void vpid_sync_vcpu_global(void)
{
if (cpu_has_vmx_invvpid_global())
__invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
}
static inline void ept_sync_global(void)
{
if (cpu_has_vmx_invept_global())
__invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
}
static inline void ept_sync_context(u64 eptp)
{
if (cpu_has_vmx_invept_context())
__invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
else
ept_sync_global();
}
static int __find_msr_index(struct vmx_vcpu *vcpu, u32 msr)
{
int i;
for (i = 0; i < vcpu->nmsrs; ++i)
if (vcpu->guest_msrs[i].index == msr)
return i;
return -1;
}
static struct msr_entry *find_msr_entry(struct vmx_vcpu *vcpu, u32 msr)
{
int i;
i = __find_msr_index(vcpu, msr);
if (i >= 0)
return &vcpu->guest_msrs[i];
return NULL;
}
#ifdef CONFIG_X86_64
static void move_msr_up(struct vmx_vcpu *vcpu, int from, int to)
{
struct msr_entry tmp;
tmp = vcpu->guest_msrs[to];
vcpu->guest_msrs[to] = vcpu->guest_msrs[from];
vcpu->guest_msrs[from] = tmp;
tmp = vcpu->host_msrs[to];
vcpu->host_msrs[to] = vcpu->host_msrs[from];
vcpu->host_msrs[from] = tmp;
}
#endif
static u32 vmx_read_guest_seg_ar(struct vmx_vcpu *vcpu, unsigned seg)
{
unsigned int ret;
vmx_get_cpu(vcpu);
ret = vmcs_read32(vmx_segment_fields[seg].ar_bytes);
vmx_put_cpu(vcpu);
return ret;
}
static int vmx_get_cpl(struct vmx_vcpu *vcpu)
{
unsigned int ar;
ar = vmx_read_guest_seg_ar(vcpu, VCPU_SREG_SS);
return VMX_AR_DPL(ar);
}
static bool __compare_msr(struct vmx_vcpu *vcpu, int n)
{
return (vcpu->guest_msrs[n].index == vcpu->host_msrs[n].index &&
vcpu->guest_msrs[n].data == vcpu->host_msrs[n].data);
}
static int __get_msr_index(struct vmx_vcpu *vcpu, u32 msr)
{
int idx;
switch (msr) {
case MSR_SYSCALL_MASK:
idx = vcpu->msr_index.sys_call_mask;
break;
case MSR_LSTAR:
idx = vcpu->msr_index.lstar;
break;
case MSR_KERNEL_GS_BASE:
idx = vcpu->msr_index.kernel_gs_base;
break;
case MSR_EFER:
idx = vcpu->msr_index.efer;
break;
case MSR_STAR:
idx = vcpu->msr_index.star;
break;
case MSR_MISC_FEATURES_ENABLES:
idx = vcpu->msr_index.feature_enable;
break;
default:
idx = __find_msr_index(vcpu, msr);
};
return idx;
}
static void load_host_msr(struct vmx_vcpu *vcpu, u32 msr)
{
int i;
i = __get_msr_index(vcpu, msr);
if (i < 0 || i >= vcpu->save_nmsrs)
return;
if (__compare_msr(vcpu, i))
return;
wrmsrl(vcpu->host_msrs[i].index, vcpu->host_msrs[i].data);
}
static void vmx_load_host_msrs(struct vmx_vcpu *vcpu)
{
int i;
if (!vcpu->guest_msrs_loaded)
return;
for (i = 0; i < NR_SHARED_MSRS; ++i)
load_host_msr(vcpu, vmx_msr_index[i]);
vcpu->guest_msrs_loaded = 0;
}
static void load_guest_msr(struct vmx_vcpu *vcpu, u32 msr)
{
int i;
i = __get_msr_index(vcpu, msr);
if (i < 0 || i >= vcpu->save_nmsrs)
return;
if (__compare_msr(vcpu, i))
return;
wrmsrl(vcpu->guest_msrs[i].index, vcpu->guest_msrs[i].data);
}
static void vmx_load_guest_msrs(struct vmx_vcpu *vcpu)
{
int i;
for (i = 0; i < NR_SHARED_MSRS; ++i)
load_guest_msr(vcpu, vmx_msr_index[i]);
vcpu->guest_msrs_loaded = 1;
}
static void save_guest_msr(struct vmx_vcpu *vcpu, u32 msr)
{
int i;
i = __get_msr_index(vcpu, msr);
if (i < 0 || i >= vcpu->save_nmsrs)
return;
rdmsrl(vcpu->guest_msrs[i].index, vcpu->guest_msrs[i].data);
}
static void save_host_msr(struct vmx_vcpu *vcpu, u32 msr)
{
int i;
i = __get_msr_index(vcpu, msr);
if (i < 0 || i >= vcpu->save_nmsrs)
return;
rdmsrl(vcpu->host_msrs[i].index, vcpu->host_msrs[i].data);
}
static void vmx_save_host_msrs(struct vmx_vcpu *vcpu)
{
int i;
for (i = 0; i < NR_SHARED_MSRS; ++i)
save_host_msr(vcpu, vmx_msr_index[i]);
}
static inline void vmx_load_guest_xcr0(struct vmx_vcpu *vcpu,
struct slimvm_config *conf)
{
if (!has_xsave)
return;
/* XCR0 cannot be set to 0. */
if (vcpu->xcr0 == 0)
return;
if (!vcpu->guest_xcr0_loaded) {
if (vcpu->xcr0 != host_xcr0)
xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->xcr0);
vcpu->guest_xcr0_loaded = 1;
}
}
static inline void vmx_put_guest_xcr0(struct vmx_vcpu *vcpu)
{
if (!has_xsave)
return;
if (vcpu->guest_xcr0_loaded) {
if (vcpu->xcr0 != host_xcr0)
xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
vcpu->guest_xcr0_loaded = 0;
}
}
static void vmx_load_host_state(struct vmx_vcpu *vcpu)
{
if (vcpu->host_state.gs_ldt_reload_needed) {
load_ldt(vcpu->host_state.ldt_sel);
load_gs_index(vcpu->host_state.gs_sel);
}
if (vcpu->host_state.fs_reload_needed)
loadsegment(fs, vcpu->host_state.fs_sel);
}
static void vmx_save_host_state(struct vmx_vcpu *vcpu)
{
unsigned long cr3, cr4;
cr3 = read_cr3();
if (unlikely(cr3 != vcpu->host_state.cr3)) {
vmcs_writel(HOST_CR3, cr3);
vcpu->host_state.cr3 = cr3;
}
cr4 = cr4_read_shadow();
if (unlikely(cr4 != vcpu->host_state.cr4)) {
vmcs_writel(HOST_CR4, cr4);
vcpu->host_state.cr4 = cr4;
}
/*
* Set host fs and gs selectors. Unfortunately, 22.2.3 does not
* allow segment selectors with cpl > 0 or ti == 1.
*/
vcpu->host_state.ldt_sel = read_ldt();
vcpu->host_state.gs_ldt_reload_needed = vcpu->host_state.ldt_sel;
savesegment(fs, vcpu->host_state.fs_sel);
if (!(vcpu->host_state.fs_sel & 7)) {
vmcs_write16(HOST_FS_SELECTOR, vcpu->host_state.fs_sel);
vcpu->host_state.fs_reload_needed = 0;
} else {
vmcs_write16(HOST_FS_SELECTOR, 0);
vcpu->host_state.fs_reload_needed = 1;
}
savesegment(gs, vcpu->host_state.gs_sel);
if (!(vcpu->host_state.gs_sel & 7))
vmcs_write16(HOST_GS_SELECTOR, vcpu->host_state.gs_sel);
else {
vmcs_write16(HOST_GS_SELECTOR, 0);
vcpu->host_state.gs_ldt_reload_needed = 1;
}
}
static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
u32 msr, u32 *result)
{
u32 vmx_msr_low, vmx_msr_high;
u32 ctl = ctl_min | ctl_opt;
rdmsr(msr, vmx_msr_low, vmx_msr_high);
ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
/* Ensure minimum (required) set of control bits are supported. */
if (ctl_min & ~ctl)
return -EIO;
*result = ctl;
return 0;
}
static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
{
u32 vmx_msr_low, vmx_msr_high;
u32 min, opt, min2, opt2;
u32 _pin_based_exec_control = 0;
u32 _cpu_based_exec_control = 0;
u32 _cpu_based_2nd_exec_control = 0;
u32 _vmexit_control = 0;
u32 _vmentry_control = 0;
min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
&_pin_based_exec_control) < 0)
return -EIO;
rdmsrl(MSR_IA32_VMX_PINBASED_CTLS, vmx_capability.pin_based);
if (vmx_capability.pin_based & (((u64)1) << 55)) {
rdmsrl(MSR_IA32_VMX_TRUE_PINBASED_CTLS, vmx_capability.pin_based);
}
min = CPU_BASED_HLT_EXITING |
#ifdef CONFIG_X86_64
CPU_BASED_CR8_LOAD_EXITING |
CPU_BASED_CR8_STORE_EXITING |
#endif
CPU_BASED_CR3_LOAD_EXITING |
CPU_BASED_CR3_STORE_EXITING |
CPU_BASED_MOV_DR_EXITING |
CPU_BASED_USE_TSC_OFFSETTING |
CPU_BASED_INVLPG_EXITING;
opt = CPU_BASED_TPR_SHADOW |
CPU_BASED_USE_MSR_BITMAPS |
CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
&_cpu_based_exec_control) < 0)
return -EIO;
#ifdef CONFIG_X86_64
if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
_cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
~CPU_BASED_CR8_STORE_EXITING;
#endif
if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
min2 = 0;
opt2 = SECONDARY_EXEC_WBINVD_EXITING |
SECONDARY_EXEC_ENABLE_VPID |
SECONDARY_EXEC_ENABLE_EPT |
SECONDARY_EXEC_ENABLE_RDTSCP |
SECONDARY_EXEC_ENABLE_INVPCID |
SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
if (adjust_vmx_controls(min2, opt2,
MSR_IA32_VMX_PROCBASED_CTLS2,
&_cpu_based_2nd_exec_control) < 0)
return -EIO;
}
if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
/* CR3 accesses and invlpg don't need to cause VM Exits when EPT
enabled */
_cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
CPU_BASED_CR3_STORE_EXITING |
CPU_BASED_INVLPG_EXITING);
rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
vmx_capability.ept, vmx_capability.vpid);
}
rdmsrl(MSR_IA32_VMX_PROCBASED_CTLS2, vmx_capability.secondary);
min = 0;
#ifdef CONFIG_X86_64
min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
#endif
opt = VM_EXIT_ACK_INTR_ON_EXIT;
if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
&_vmexit_control) < 0)
return -EIO;
min = 0;
opt = 0;
if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
&_vmentry_control) < 0)
return -EIO;
rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
/* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
return -EIO;
#ifdef CONFIG_X86_64
/* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
if (vmx_msr_high & (1u<<16))
return -EIO;
#endif
/* Require Write-Back (WB) memory type for VMCS accesses. */
if (((vmx_msr_high >> 18) & 15) != 6)
return -EIO;
vmcs_conf->size = vmx_msr_high & 0x1fff;
vmcs_conf->order = get_order(vmcs_config.size);
vmcs_conf->revision_id = vmx_msr_low;
/* filter all of the IO ports */
_cpu_based_exec_control |= CPU_BASED_UNCOND_IO_EXITING;
_cpu_based_exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
vmcs_conf->vmexit_ctrl = _vmexit_control;
vmcs_conf->vmentry_ctrl = _vmentry_control;
return 0;
}
static struct vmcs *__vmx_alloc_vmcs(int cpu)
{
int node = cpu_to_node(cpu);
struct page *pages;
struct vmcs *vmcs;
pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
if (!pages)
return NULL;
vmcs = page_address(pages);
memset(vmcs, 0, vmcs_config.size);
vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
return vmcs;
}
/**
* vmx_alloc_vmcs - allocates a VMCS region
*
* NOTE: Assumes the new region will be used by the current CPU.
*
* Returns a valid VMCS region.
*/
static struct vmcs *vmx_alloc_vmcs(void)
{
return __vmx_alloc_vmcs(raw_smp_processor_id());
}
/**
* vmx_free_vmcs - frees a VMCS region
*/
static void vmx_free_vmcs(struct vmcs *vmcs)
{
free_pages((unsigned long)vmcs, vmcs_config.order);
}
/*
* Set up the vmcs's constant host-state fields, i.e., host-state fields that
* will not change in the lifetime of the guest.
* Note that host-state that does change is set elsewhere. E.g., host-state
* that is set differently for each CPU is set in vmx_vcpu_load(), not here.
*/
static void vmx_setup_constant_host_state(struct vmx_vcpu *vcpu)
{
u32 low32, high32;
unsigned long host_rip;
vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
vmcs_writel(HOST_CR4, __read_cr4()); /* 22.2.3, 22.2.5 */
vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 */
vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
vmcs_writel(HOST_IDTR_BASE, (unsigned long)vcpu->idt_base); /* 22.2.4 */
asm("mov $.Lkvm_vmx_return, %0" : "=r"(host_rip));
vmcs_writel(HOST_RIP, host_rip);
rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
vmcs_writel(HOST_IA32_SYSENTER_EIP, read_msr(MSR_IA32_SYSENTER_EIP));
if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
rdmsr(MSR_IA32_CR_PAT, low32, high32);
vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
}
vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
#ifdef CONFIG_X86_64
vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
#else
vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
#endif
}
static void __vmx_get_cpu_helper(void *ptr)
{
struct vmx_vcpu *vcpu = ptr;
WARN_ON(raw_smp_processor_id() != vcpu->cpu);
vmcs_clear(vcpu->vmcs);
if (__this_cpu_read(local_vcpu) == vcpu)
this_cpu_write(local_vcpu, NULL);
}
static void __load_vcpu(struct vmx_vcpu *vcpu, int cpu)
{
if (__this_cpu_read(local_vcpu) != vcpu) {
this_cpu_write(local_vcpu, vcpu);
if (vcpu->cpu != cpu) {
unsigned long sysenter_esp;
if (vcpu->cpu >= 0)
smp_call_function_single(vcpu->cpu,
__vmx_get_cpu_helper, (void *) vcpu, 1);
vmx_make_request(VMX_REQ_TLB_FLUSH, vcpu);
vcpu->launched = 0;
vmcs_load(vcpu->vmcs);
/*
* Linux uses per-cpu TSS and GDT, so set these when switching
* processors.
*/
vmcs_writel(HOST_TR_BASE, vmx_read_tr_base(cpu));
vmcs_writel(HOST_GDTR_BASE, vmx_read_gdt_addr());
rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp);
vcpu->cpu = cpu;
} else
vmcs_load(vcpu->vmcs);
}
}
static void __put_vcpu(struct vmx_vcpu *vcpu)
{
vmx_invalidate_tss_limit();
vmx_load_fixmap_gdt();
}
/**
* vmx_get_cpu - called before using a cpu
* @vcpu: VCPU that will be loaded.
*
* Disables preemption. Call vmx_put_cpu() when finished.
*/
void vmx_get_cpu(struct vmx_vcpu *vcpu)
{
int cpu = get_cpu();
__load_vcpu(vcpu, cpu);
}
/**
* vmx_put_cpu - called after using a cpu
* @vcpu: VCPU that was loaded.
*/
void vmx_put_cpu(struct vmx_vcpu *vcpu)
{
put_cpu();
}
void vmx_set_vcpu_mode(struct vmx_vcpu *vcpu, u8 mode)
{
vcpu->mode = mode;
smp_wmb();
}
bool vmx_check_vcpu_mode(struct vmx_vcpu *vcpu, u8 mode)
{
return (vcpu->mode == mode);
}
static void slimvm_sched_in(struct preempt_notifier *pn, int cpu)
{
struct vmx_vcpu *vcpu = container_of(pn, struct vmx_vcpu,
preempt_notifier);
vmx_save_host_msrs(vcpu);
__load_vcpu(vcpu, cpu);
this_cpu_write(vmx_current_vcpu, vcpu);
vcpu->scheded = 1;
vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
}
static void slimvm_sched_out(struct preempt_notifier *pn,
struct task_struct *next)
{
struct vmx_vcpu *vcpu = container_of(pn, struct vmx_vcpu,
preempt_notifier);
__put_vcpu(vcpu);
this_cpu_write(vmx_current_vcpu, NULL);
vmx_load_host_msrs(vcpu);
vmx_put_guest_xcr0(vcpu);
}
static void __vmx_vcpu_kick(void *p)
{
}
void vmx_shutdown_all_vcpus(struct instance *instp)
{
int vcpu_no, cpu, me;
struct vmx_vcpu *vcpu;
cpumask_var_t cpus;
zalloc_cpumask_var(&cpus, GFP_ATOMIC);
me = get_cpu();
spin_lock(&instp->vcpu_lock);
for_each_set_bit(vcpu_no, instp->vcpu_bitmap, VM_MAX_VCPUS) {
vcpu = instp->vcpus[vcpu_no];
if (!vcpu)
continue;
vcpu->shutdown = 1;
cpu = vcpu->cpu;
if (cpus != NULL && cpu != -1 && cpu != me &&
!vmx_check_vcpu_mode(vcpu, OUTSIDE_ROOT_MODE))
cpumask_set_cpu(cpu, cpus);
}
spin_unlock(&instp->vcpu_lock);
if (unlikely(cpus == NULL)) {
smp_call_function_many(cpu_online_mask,
__vmx_vcpu_kick, NULL, 1);
} else if (!cpumask_empty(cpus)) {
smp_call_function_many(cpus,
__vmx_vcpu_kick, NULL, 1);
}
instp->shutdown = 1;
put_cpu();
free_cpumask_var(cpus);
}
void vmx_sync_all_vcpus(struct instance *instp)
{
struct vmx_vcpu *vcpu;
int vcpu_no;
while (true) {
bool r = true;
spin_lock(&instp->vcpu_lock);
for_each_set_bit(vcpu_no, instp->vcpu_bitmap,
VM_MAX_VCPUS) {
vcpu = instp->vcpus[vcpu_no];
if (!vcpu)
continue;
r &= vmx_check_vcpu_mode(vcpu, OUTSIDE_ROOT_MODE);
}
spin_unlock(&instp->vcpu_lock);
if (r)
break;
}
}
static void vmx_dump_sel(char *name, uint32_t sel)
{
pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
name, vmcs_read32(sel),
vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
}
static void vmx_dump_dtsel(char *name, uint32_t limit)
{
pr_err("%s limit=0x%08x, base=0x%016lx\n",
name, vmcs_read32(limit),
vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
}
/**
* vmx_dump_cpu - prints the CPU state
* @vcpu: VCPU to print
*/
static void vmx_dump_cpu(struct vmx_vcpu *vcpu)