Simulation Issue with MSI-X Interrupts in PTILE

[2117209]

When the hardware MSI-X capability is 64 and the software requests 32 interrupts, with IRQ_INDEX_WIDTH=5 in the example_core_pcie module, the first 32 interrupt vectors initialize correctly. However, the 33rd interrupt vector causes a wrap-around in tbl_mem (MSI-X table), leading to an incorrect interrupt vector number.

In the cocotbext/pcie/core/pci.py code, should the msix_capability_init function first evaluate the table_size and nvec variables and choose the smaller one to initialize the MSI-X table? Or, after determining the number of interrupts, should the IRQ_INDEX_WIDTH parameter in example_core_pcie be manually modified?