[AIEPlacer] Tighten capacity check: shared helper, stack, MemTile, diagnostics

Address review on PR #3044:

* Lift the CoreTile/MemTile capacity dispatch into a single
  `AIETargetModel::getDataMemorySize(AIETileType)` helper. Both
  AIEAssignBuffers (basic + bank-aware) and the placer now consume it,
  removing three copies of the same dispatch.

* Reserve `core.getStackSize()` per CoreTile LogicalTileOp at requirement-
  build time. AIEAssignBuffers reserves the stack before laying out
  buffers; the placer now matches that, so a CoreTile candidate that
  passes here also fits at allocation time.

* Validate the per-LogicalTileOp upper bound for MemTiles too. Full
  per-physical-tile accumulation across MemTile-sharing LogicalTileOps
  is still left to AIEAssignBuffers (the channel-style accumulator is a
  separate follow-up), but the necessary single-tile bound is now
  caught here with the better diagnostic.

* Track in the partial-constraint loop whether buffer capacity was the
  *only* reason candidates matching `col`/`row` were skipped, so the
  unconstrained-failure suffix names buffer capacity only when that was
  the actual cause. Document that on current homogeneous devices the
  per-candidate buffer filter is forward-looking - all CoreTiles share
  one capacity - so its purpose today is to feed the diagnostic.

* Switch `tileMemoryCapacity` to `int64_t`, matching `getAllocationSize`
  and removing the `static_cast<uint64_t>` workaround.

* Diagnostic now distinguishes "buffers + stack" (CoreTile) from
  "buffers" (MemTile), with the bytes-vs-capacity numbers reflecting
  the actual demand including stack.

* Tests: add multi-buffer summation, physical-tile peer skip, MemTile
  pinned fits/overflow, and an AIE2P/npu2 path. Update the existing
  error wording / overflow byte counts for the stack-aware demand.

* Document the remaining limitations in code comments: ObjectFifo-
  derived buffers are not yet visible at this pass and remain
  AIEAssignBuffers' responsibility; mid-migration mixed physical/
  logical IR is validated only for the LogicalTileOp share.

All 137 lit tests pass under test/place-tiles, test/dialect/AIE,
test/assign-buffer-addresses (1 pre-existing XFAIL); mlir-air rebuilds
clean against the updated shared library.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

Author: erwei-xilinx

include/aie/Dialect/AIE/IR/AIETargetModel.h

@@ -257,6 +257,12 @@ class AIETargetModel {
   /// Return the size (in bytes) of the local data memory of a core.
   virtual uint32_t getLocalMemorySize() const = 0;
 
+  /// Return the size (in bytes) of the data memory addressable from the given
+  /// tile type: `getLocalMemorySize()` for CoreTile, `getMemTileSize()` for
+  /// MemTile, 0 otherwise. Centralizes the dispatch used by AIEAssignBuffers
+  /// and AIEPlacer so per-tile-type capacity stays consistent across passes.
+  uint32_t getDataMemorySize(AIETileType tileType) const;
+
   /// Return the size (in bits) of the accumulator/cascade.
   virtual uint32_t getAccumulatorCascadeSize() const = 0;
 

include/aie/Dialect/AIE/Transforms/AIEPlacer.h

@@ -114,19 +114,28 @@ class SequentialPlacer : public Placer {
       llvm::SmallVector<ObjectFifoCreateOp> &objectFifos,
       llvm::SmallVector<ObjectFifoLinkOp> &objectFifoLinks);
 
-  // Sum `BufferOp::getAllocationSize()` per `LogicalTileOp` (TileOp peers are
-  // physical and validated downstream by AIEAssignBuffers).
+  // Sum `BufferOp::getAllocationSize()` per `LogicalTileOp`, plus the stack
+  // reservation of any attached CoreOp for CoreTile LogicalTileOps (matching
+  // AIEAssignBuffers' downstream layout). Buffers attached to physical TileOp
+  // peers are skipped: those are not part of any placement decision and are
+  // still validated downstream by AIEAssignBuffers. ObjectFifo-derived buffers
+  // are not yet visible at this pass and are not counted; AIEAssignBuffers
+  // remains the authoritative final check.
   llvm::DenseMap<mlir::Operation *, int64_t>
-  buildBufferRequirements(llvm::ArrayRef<BufferOp> buffers);
+  buildBufferRequirements(llvm::ArrayRef<BufferOp> buffers,
+                          llvm::ArrayRef<LogicalTileOp> logicalTiles);
 
   // Returns true iff placing `logicalTile` at `candidate` would keep its total
-  // buffer allocation within the candidate tile type's local memory capacity.
+  // buffer allocation (plus stack reservation, for CoreTiles) within the
+  // candidate tile type's data memory capacity. Returns true unconditionally
+  // for tile types without addressable data memory (Shim*).
   bool fitsBufferCapacity(LogicalTileOp logicalTile, TileID candidate,
                           const llvm::DenseMap<mlir::Operation *, int64_t>
                               &bufferRequirements) const;
 
-  // Capacity in bytes for the given physical tile (0 if no local memory).
-  uint32_t tileMemoryCapacity(TileID tile) const;
+  // Data memory capacity in bytes for the given physical tile (0 if the tile
+  // has no addressable data memory).
+  int64_t tileMemoryCapacity(TileID tile) const;
 };
 
 } // namespace xilinx::AIE

lib/Dialect/AIE/IR/AIETargetModel.cpp

@@ -84,6 +84,19 @@ uint32_t AIETargetModel::encodeFieldValue(const BitFieldInfo &field,
   return db->encodeFieldValue(field, value);
 }
 
+uint32_t AIETargetModel::getDataMemorySize(AIETileType tileType) const {
+  switch (tileType) {
+  case AIETileType::CoreTile:
+    return getLocalMemorySize();
+  case AIETileType::MemTile:
+    return getMemTileSize();
+  case AIETileType::ShimNOCTile:
+  case AIETileType::ShimPLTile:
+    return 0;
+  }
+  llvm_unreachable("unhandled AIETileType");
+}
+
 std::optional<uint32_t>
 AIETargetModel::getFieldMask(const BitFieldInfo &field) const {
   uint32_t width = field.getWidth();

lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp

@@ -61,11 +61,7 @@ bool basicAllocation(TileOp tile) {
     return false;
 
   const auto &targetModel = getTargetModel(tile);
-  int maxDataMemorySize = 0;
-  if (tile.isMemTile())
-    maxDataMemorySize = targetModel.getMemTileSize();
-  else
-    maxDataMemorySize = targetModel.getLocalMemorySize();
+  int maxDataMemorySize = targetModel.getDataMemorySize(tile.getTileType());
 
   SmallVector<BufferOp> buffers;
   SmallVector<BufferOp> allocated_buffers;
@@ -386,11 +382,7 @@ bool simpleBankAwareAllocation(TileOp tile) {
                                       // end addresses for each bank
 
   const auto &targetModel = getTargetModel(tile);
-  int maxDataMemorySize = 0;
-  if (tile.isMemTile())
-    maxDataMemorySize = targetModel.getMemTileSize();
-  else
-    maxDataMemorySize = targetModel.getLocalMemorySize();
+  int maxDataMemorySize = targetModel.getDataMemorySize(tile.getTileType());
 
   int numBanks = targetModel.getNumBanks(tile.getCol(), tile.getRow());
   int bankSize = maxDataMemorySize / numBanks;

lib/Dialect/AIE/Transforms/AIEPlacer.cpp

@@ -137,7 +137,7 @@ LogicalResult SequentialPlacer::place(DeviceOp device) {
   // tile-local memory requirements from BufferOp allocations.
   auto channelRequirements =
       buildChannelRequirements(objectFifos, objectFifoLinks);
-  auto bufferRequirements = buildBufferRequirements(buffers);
+  auto bufferRequirements = buildBufferRequirements(buffers, logicalTiles);
 
   // Phase 3: Place constrained tiles then compute tiles
   size_t nextCompIdx = 0;
@@ -149,9 +149,14 @@ LogicalResult SequentialPlacer::place(DeviceOp device) {
       TileID tile{*col, *row};
       if (!fitsBufferCapacity(logicalTile, tile, bufferRequirements)) {
         int64_t need = bufferRequirements.lookup(logicalTile.getOperation());
+        // Stack only contributes when this LogicalTileOp is a CoreTile with
+        // an attached CoreOp; mention it only in that case for accuracy.
+        bool includesStack =
+            logicalTile.getTileType() == AIETileType::CoreTile;
         return logicalTile.emitError()
                << "tile (" << tile.col << ", " << tile.row << ") cannot host "
-               << need << " bytes of buffers (capacity "
+               << need << " bytes of buffers"
+               << (includesStack ? " + stack" : "") << " (capacity "
                << tileMemoryCapacity(tile) << ")";
       }
       if (failed(validateAndUpdateChannelUsage(logicalTile, tile,
@@ -170,6 +175,15 @@ LogicalResult SequentialPlacer::place(DeviceOp device) {
     // Place compute tiles with partial constraint support
     if (logicalTile.getTileType() == AIETileType::CoreTile) {
       std::optional<TileID> placement = std::nullopt;
+      // Track whether buffer capacity was the *only* reason candidates
+      // matching the partial constraints (if any) were skipped, so the
+      // diagnostic on failure can name the actual cause. (On current devices
+      // every CoreTile has the same `getLocalMemorySize()`, so skipping one
+      // by buffer-capacity skips them all - this loop's per-candidate filter
+      // is forward-looking for heterogeneous future devices and feeds the
+      // diagnostic below.)
+      bool sawConstraintMatch = false;
+      bool allConstraintMatchesFailedBuffer = true;
 
       for (size_t i = nextCompIdx; i < availability.compTiles.size(); ++i) {
         TileID candidate = availability.compTiles[i];
@@ -179,8 +193,10 @@ LogicalResult SequentialPlacer::place(DeviceOp device) {
           continue;
         if (row && candidate.row != *row)
           continue;
+        sawConstraintMatch = true;
         if (!fitsBufferCapacity(logicalTile, candidate, bufferRequirements))
           continue;
+        allConstraintMatchesFailedBuffer = false;
 
         // Found valid tile - swap to nextCompIdx position and use
         std::swap(availability.compTiles[i],
@@ -190,17 +206,24 @@ LogicalResult SequentialPlacer::place(DeviceOp device) {
       }
 
       if (!placement) {
-        bool hasBuffers = bufferRequirements.count(logicalTile.getOperation());
+        // Buffer capacity is implicated only when at least one candidate
+        // matched the partial constraints AND every such candidate failed the
+        // buffer filter.
+        bool bufferWasCause =
+            sawConstraintMatch && allConstraintMatchesFailedBuffer &&
+            bufferRequirements.count(logicalTile.getOperation());
         if (col || row) {
           return logicalTile.emitError()
                  << "no compute tile available matching constraint ("
                  << (col ? std::to_string(*col) : "?") << ", "
                  << (row ? std::to_string(*row) : "?") << ")"
-                 << (hasBuffers ? " and buffer capacity" : "");
+                 << (bufferWasCause ? " with sufficient buffer capacity" : "");
         }
         return logicalTile.emitError()
                << "no available compute tiles for placement"
-               << (hasBuffers ? " (buffer capacity exceeded)" : "");
+               << (bufferWasCause ? " (buffer capacity exceeded on every "
+                                    "candidate)"
+                                  : "");
       }
 
       if (failed(validateAndUpdateChannelUsage(logicalTile, *placement,
@@ -488,46 +511,71 @@ SequentialPlacer::buildChannelRequirements(
   return channelRequirements;
 }
 
-llvm::DenseMap<Operation *, int64_t>
-SequentialPlacer::buildBufferRequirements(ArrayRef<BufferOp> buffers) {
+// Sum BufferOp::getAllocationSize() per LogicalTileOp, then add the stack
+// reservation of any CoreOp attached to that LogicalTileOp. The stack lives in
+// the same local data memory as buffers (cf. AIEAssignBuffers reserving
+// `core.getStackSize()` bytes before laying out buffers), so a CoreTile
+// candidate that passes the placer must also leave room for the stack.
+//
+// Buffers attached to physical TileOps are skipped here: those are not part of
+// any placement decision and are still validated downstream by
+// AIEAssignBuffers. Mid-migration IR mixing physical TileOp and LogicalTileOp
+// peers on the same eventual physical tile is therefore validated only for the
+// LogicalTileOp share at this stage; AIEAssignBuffers catches the rest.
+//
+// ObjectFifo-derived buffers are not yet visible at this pass (they are
+// materialized later by objectfifo lowering) and are not counted here. A tile
+// that passes this filter can still overflow once those buffers materialize;
+// AIEAssignBuffers remains the authoritative final check.
+llvm::DenseMap<Operation *, int64_t> SequentialPlacer::buildBufferRequirements(
+    ArrayRef<BufferOp> buffers, ArrayRef<LogicalTileOp> logicalTiles) {
   llvm::DenseMap<Operation *, int64_t> bufferRequirements;
+
+  // Seed with stack reservations for CoreTile LogicalTileOps that already
+  // have a CoreOp user. Without a CoreOp the stack attribute does not yet
+  // exist, so don't pre-reserve.
+  for (auto lt : logicalTiles) {
+    if (lt.getTileType() != AIETileType::CoreTile)
+      continue;
+    for (Operation *user : lt.getResult().getUsers()) {
+      if (auto core = dyn_cast<CoreOp>(user)) {
+        bufferRequirements[lt.getOperation()] += core.getStackSize();
+        break;
+      }
+    }
+  }
+
   for (auto buf : buffers) {
     auto *defOp = buf.getTile().getDefiningOp();
-    // Only LogicalTileOp endpoints participate in placement decisions.
-    // TileOp peers are physical and validated downstream by AIEAssignBuffers.
     if (!isa_and_nonnull<LogicalTileOp>(defOp))
       continue;
     bufferRequirements[defOp] += buf.getAllocationSize();
   }
   return bufferRequirements;
 }
 
-uint32_t SequentialPlacer::tileMemoryCapacity(TileID tile) const {
-  switch (targetModel->getTileType(tile.col, tile.row)) {
-  case AIETileType::CoreTile:
-    return targetModel->getLocalMemorySize();
-  case AIETileType::MemTile:
-    return targetModel->getMemTileSize();
-  default:
-    return 0;
-  }
+int64_t SequentialPlacer::tileMemoryCapacity(TileID tile) const {
+  return targetModel->getDataMemorySize(
+      targetModel->getTileType(tile.col, tile.row));
 }
 
 bool SequentialPlacer::fitsBufferCapacity(
     LogicalTileOp logicalTile, TileID candidate,
     const llvm::DenseMap<Operation *, int64_t> &bufferRequirements) const {
-  // MemTiles are shared across LogicalTileOps in the existing placer (see
-  // `removeTile` skipping non-CoreTile). Validating accumulated buffer bytes
-  // there requires per-physical-tile tracking (cf. inputChannelsUsed); leave
-  // that to AIEAssignBuffers and a follow-up PR. CoreTiles are 1:1 so the
-  // per-LogicalTileOp sum is the actual physical-tile demand.
-  if (targetModel->getTileType(candidate.col, candidate.row) !=
-      AIETileType::CoreTile)
+  // Both CoreTile and MemTile have finite data memory. CoreTile is 1:1 with a
+  // LogicalTileOp, so the per-LogicalTileOp sum *is* the physical-tile demand
+  // and we validate exactly. MemTile may host buffers from multiple
+  // LogicalTileOps (cf. `removeTile` skipping non-CoreTile and the channel
+  // accumulation in `inputChannelsUsed`); we still validate the per-tile sum
+  // as a *necessary* upper bound here, but full per-physical-tile accumulation
+  // is left to AIEAssignBuffers and a follow-up PR.
+  AIETileType type = targetModel->getTileType(candidate.col, candidate.row);
+  if (type != AIETileType::CoreTile && type != AIETileType::MemTile)
     return true;
   auto it = bufferRequirements.find(logicalTile.getOperation());
   if (it == bufferRequirements.end())
     return true;
-  return static_cast<uint64_t>(it->second) <= tileMemoryCapacity(candidate);
+  return it->second <= tileMemoryCapacity(candidate);
 }
 
 void SequentialPlacer::buildObjectFifoGroups(

test/place-tiles/sequential_placer/test_place_buffers.mlir

@@ -36,3 +36,76 @@ module @buffer_fits_unconstrained {
     // CHECK-NOT: aie.logical_tile
   }
 }
+
+// -----
+
+// Multiple buffers on the same logical tile sum together against capacity.
+// 4 * memref<8192xi32> = 4 * 32KB = 128KB of buffers + 1KB stack would exceed
+// npu1's 64KB CoreTile L1, but each buffer is 32KB on its own. This case uses
+// 3 * 8KB = 24KB + 1KB stack = 25KB which fits comfortably; it pins the
+// summation behaviour without overflowing.
+// CHECK-LABEL: @multi_buffer_sum_fits
+module @multi_buffer_sum_fits {
+  aie.device(npu1) {
+    // CHECK-DAG: %[[T:.*]] = aie.tile(2, 3)
+    %t = aie.logical_tile<CoreTile>(2, 3)
+    %b0 = aie.buffer(%t) : memref<2048xi32>
+    %b1 = aie.buffer(%t) : memref<2048xi32>
+    %b2 = aie.buffer(%t) : memref<2048xi32>
+    aie.core(%t) { aie.end }
+    // CHECK-NOT: aie.logical_tile
+  }
+}
+
+// -----
+
+// Buffer attached to a physical aie.tile (not aie.logical_tile) is silently
+// ignored by the placer's buffer-capacity check: such buffers are not part of
+// any placement decision and remain AIEAssignBuffers' responsibility. The
+// 256KB physical-tile buffer here would overflow if it were counted, but the
+// placer must accept this IR unchanged (a separate logical_tile with a small
+// buffer placed normally proves the rest of the pipeline still runs).
+// CHECK-LABEL: @physical_tile_buffer_skipped
+module @physical_tile_buffer_skipped {
+  aie.device(npu1) {
+    // CHECK-DAG: %[[PT:.*]] = aie.tile(2, 3)
+    %pt = aie.tile(2, 3)
+    %big = aie.buffer(%pt) : memref<65536xi32>
+    // CHECK-DAG: %[[LT:.*]] = aie.tile(2, 4)
+    %lt = aie.logical_tile<CoreTile>(2, 4)
+    %small = aie.buffer(%lt) : memref<128xi32>
+    aie.core(%lt) { aie.end }
+    // CHECK-NOT: aie.logical_tile
+  }
+}
+
+// -----
+
+// MemTile-pinned LogicalTileOp with a buffer that fits in the MemTile capacity
+// (npu1 MemTile = 512KB). Validates that MemTile placements pass the new
+// per-LogicalTileOp upper-bound check.
+// CHECK-LABEL: @memtile_buffer_fits
+module @memtile_buffer_fits {
+  aie.device(npu1) {
+    // CHECK-DAG: %[[MT:.*]] = aie.tile(0, 1)
+    %mt = aie.logical_tile<MemTile>(0, 1)
+    %b = aie.buffer(%mt) : memref<1024xi32>
+    // CHECK-NOT: aie.logical_tile
+  }
+}
+
+// -----
+
+// Same shape on AIE2P (npu2), exercising the target-model dispatch on a
+// different architecture. npu2 CoreTile L1 is also 64KB; a 4KB buffer plus
+// 1KB default stack fits with room to spare.
+// CHECK-LABEL: @buffer_fits_npu2
+module @buffer_fits_npu2 {
+  aie.device(npu2) {
+    // CHECK-DAG: %[[T:.*]] = aie.tile(0, 2)
+    %t = aie.logical_tile<CoreTile>(?, ?)
+    %b = aie.buffer(%t) : memref<1024xi32>
+    aie.core(%t) { aie.end }
+    // CHECK-NOT: aie.logical_tile
+  }
+}