From the RP2040 datasheet:
2.1.2. Atomic Register Access
Each peripheral register block is allocated 4kB of address space, with registers accessed using one of 4 methods,
selected by address decode.
• Addr + 0x0000 : normal read write access
• Addr + 0x1000 : atomic XOR on write
• Addr + 0x2000 : atomic bitmask set on write
• Addr + 0x3000 : atomic bitmask clear on write
Currently, rp2040_hal only uses the normal read write access alias. It might make sense to use the atomic aliases for some operations, but these should be used sparingly. I'd really prefer that concurrent access be mediated by Ravenscar's protected types or the SIO's semaphores.
This needs more investigation to determine the tradeoffs.
From the RP2040 datasheet:
Currently, rp2040_hal only uses the normal read write access alias. It might make sense to use the atomic aliases for some operations, but these should be used sparingly. I'd really prefer that concurrent access be mediated by Ravenscar's protected types or the SIO's semaphores.
This needs more investigation to determine the tradeoffs.