verilog-model/verilog-model.ipkg at master · DepTyCheck/verilog-model · GitHub

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package verilog-model
brief = "DepTyCheck model of SystemVerilog"

authors = "Denis Buzdalov"

license = "Apache-2.0"

sourcedir = "src"
builddir = ".build"

version = 0.1.0
langversion >= 0.7.0

executable = verilog-model
main = Runner

prebuild = "sh .derive-in-parallel"

depends = collection-utils
        , deptycheck >= 0.0.250305
        , getopts
        , i-hate-parens
        , prettier
        , fin-lizzie

modules = Test.Common.Utils
        , Test.Common.DataType
        , Test.Common.UniqueFins
        , Test.Common.UniqueFins.Derived
        , Test.Common.UniqueNames
        , Test.Common.UniqueNames.Derived

        , Test.Verilog.SVType
        , Test.Verilog.Assign
        , Test.Verilog.Literal
        , Test.Verilog.TMPExpression
        , Test.Verilog.Warnings
        , Test.Verilog.UniqueNames
        , Test.Verilog.Defaults
        , Test.Verilog.SVDesign

        , Test.Verilog.TMPExpression.Derived

        , Test.Common.UniqueNames
        , Test.Common.UniqueNames.Derived

        , Test.VHDL.UniqueNames
        , Test.VHDL.Defaults
        , Test.VHDL.VHDLType

        , Test.Common.Design
        , Test.Common.Design.Derived

        , Test.VHDL.VHDLDesign

        , Test.Common.Gen

        , Test.Common.PrintableDesigns
        , Test.Verilog.Pretty
        , Test.VHDL.Pretty
        , Test.Common.Pretty