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2869 lines (2609 loc) · 202 KB
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2025.2 (win64) Build 6299465 Fri Nov 14 19:35:11 GMT 2025
| Date : Fri Dec 26 14:23:55 2025
| Host : hua running 64-bit major release (build 9200)
| Command : report_timing_summary -max_paths 10 -routable_nets -report_unconstrained -file top_timing_summary_routed.rpt -pb top_timing_summary_routed.pb -rpx top_timing_summary_routed.rpx -warn_on_violation
| Design : top
| Device : 7a100t-csg324
| Speed File : -1 PRODUCTION 1.23 2018-06-13
| Design State : Routed
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Timing Summary Report
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
Rule Severity Description Violations
--------- -------- ----------------------------- ----------
TIMING-18 Warning Missing input or output delay 16
Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.
check_timing report
Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (1)
6. checking no_output_delay (9)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (0)
------------------------
There are 0 register/latch pins with no clock.
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
There are 0 pins that are not constrained for maximum delay.
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (1)
------------------------------
There is 1 input port with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (9)
-------------------------------
There are 9 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
4.844 0.000 0 268 0.051 0.000 0 268 3.750 0.000 0 131
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sys_clk_pin {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clk_pin 4.844 0.000 0 268 0.051 0.000 0 268 3.750 0.000 0 131
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| User Ignored Path Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock
---------- ---------- --------
------------------------------------------------------------------------------------------------
| Unconstrained Path Table
| ------------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock
---------- ---------- --------
(none) sys_clk_pin
(none) sys_clk_pin
------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
From Clock: sys_clk_pin
To Clock: sys_clk_pin
Setup : 0 Failing Endpoints, Worst Slack 4.844ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.051ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 3.750ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 4.844ns (required time - arrival time)
Source: CPU/CPU_ID_EX/EX_imm_reg[2]/C
(rising edge-triggered cell FDRE clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Destination: CPU/CPU_EX_MEM/MEM_zero_flag_reg/D
(rising edge-triggered cell FDRE clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Path Group: sys_clk_pin
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (sys_clk_pin [email protected] - sys_clk_pin [email protected])
Data Path Delay: 5.045ns (logic 1.979ns (39.226%) route 3.066ns (60.774%))
Logic Levels: 6 (CARRY4=2 LUT4=1 LUT5=3)
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.027ns = ( 15.027 - 10.000 )
Source Clock Delay (SCD): 5.311ns
Clock Pessimism Removal (CPR): 0.180ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
0.000 0.000 r
E3 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 clk
E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O
net (fo=1, routed) 2.025 3.506 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 1.709 5.311 CPU/CPU_ID_EX/clk_IBUF_BUFG
SLICE_X5Y101 FDRE r CPU/CPU_ID_EX/EX_imm_reg[2]/C
------------------------------------------------------------------- -------------------
SLICE_X5Y101 FDRE (Prop_fdre_C_Q) 0.456 5.767 r CPU/CPU_ID_EX/EX_imm_reg[2]/Q
net (fo=11, routed) 1.148 6.915 CPU/CPU_ID_EX/Q[1]
SLICE_X3Y98 LUT4 (Prop_lut4_I1_O) 0.124 7.039 r CPU/CPU_ID_EX/temp0_carry_i_4/O
net (fo=1, routed) 0.000 7.039 CPU/CPU_ALU/S[0]
SLICE_X3Y98 CARRY4 (Prop_carry4_S[0]_CO[3])
0.532 7.571 r CPU/CPU_ALU/temp0_carry/CO[3]
net (fo=1, routed) 0.000 7.571 CPU/CPU_ALU/temp0_carry_n_0
SLICE_X3Y99 CARRY4 (Prop_carry4_CI_O[3])
0.313 7.884 f CPU/CPU_ALU/temp0_carry__0/O[3]
net (fo=1, routed) 0.621 8.505 CPU/CPU_ID_EX/data0[7]
SLICE_X4Y100 LUT5 (Prop_lut5_I0_O) 0.306 8.811 f CPU/CPU_ID_EX/MEM_alu_result[7]_i_1/O
net (fo=2, routed) 0.853 9.663 CPU/CPU_ID_EX/EX_neg_flag
SLICE_X4Y100 LUT5 (Prop_lut5_I1_O) 0.124 9.787 r CPU/CPU_ID_EX/MEM_zero_flag_i_2/O
net (fo=1, routed) 0.445 10.232 CPU/CPU_ID_EX/MEM_zero_flag_i_2_n_0
SLICE_X4Y99 LUT5 (Prop_lut5_I0_O) 0.124 10.356 r CPU/CPU_ID_EX/MEM_zero_flag_i_1/O
net (fo=1, routed) 0.000 10.356 CPU/CPU_EX_MEM/MEM_zero_flag_reg_0
SLICE_X4Y99 FDRE r CPU/CPU_EX_MEM/MEM_zero_flag_reg/D
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
10.000 10.000 r
E3 0.000 10.000 r clk (IN)
net (fo=0) 0.000 10.000 clk
E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r clk_IBUF_inst/O
net (fo=1, routed) 1.920 13.331 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 1.604 15.027 CPU/CPU_EX_MEM/clk_IBUF_BUFG
SLICE_X4Y99 FDRE r CPU/CPU_EX_MEM/MEM_zero_flag_reg/C
clock pessimism 0.180 15.207
clock uncertainty -0.035 15.171
SLICE_X4Y99 FDRE (Setup_fdre_C_D) 0.029 15.200 CPU/CPU_EX_MEM/MEM_zero_flag_reg
-------------------------------------------------------------------
required time 15.200
arrival time -10.356
-------------------------------------------------------------------
slack 4.844
Slack (MET) : 5.421ns (required time - arrival time)
Source: CPU/CPU_IF_ID/ID_instruction_reg[14]/C
(rising edge-triggered cell FDRE clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Destination: CPU/CPU_ID_EX/EX_reg_data_2_reg[4]/D
(rising edge-triggered cell FDRE clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Path Group: sys_clk_pin
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (sys_clk_pin [email protected] - sys_clk_pin [email protected])
Data Path Delay: 4.516ns (logic 1.151ns (25.490%) route 3.365ns (74.510%))
Logic Levels: 3 (LUT2=1 LUT5=1 RAMD32=1)
Clock Path Skew: -0.103ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.029ns = ( 15.029 - 10.000 )
Source Clock Delay (SCD): 5.311ns
Clock Pessimism Removal (CPR): 0.180ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
0.000 0.000 r
E3 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 clk
E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O
net (fo=1, routed) 2.025 3.506 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 1.709 5.311 CPU/CPU_IF_ID/clk_IBUF_BUFG
SLICE_X6Y100 FDRE r CPU/CPU_IF_ID/ID_instruction_reg[14]/C
------------------------------------------------------------------- -------------------
SLICE_X6Y100 FDRE (Prop_fdre_C_Q) 0.518 5.829 r CPU/CPU_IF_ID/ID_instruction_reg[14]/Q
net (fo=8, routed) 1.092 6.921 CPU/CPU_IF_ID/ID_instruction[14]
SLICE_X4Y100 LUT5 (Prop_lut5_I2_O) 0.124 7.045 r CPU/CPU_IF_ID/registers_reg_r2_0_3_0_5_i_1/O
net (fo=8, routed) 1.464 8.509 CPU/CPU_Register_File/registers_reg_r2_0_3_0_5/ADDRC0
SLICE_X2Y99 RAMD32 (Prop_ramd32_RADR0_O)
0.153 8.662 r CPU/CPU_Register_File/registers_reg_r2_0_3_0_5/RAMC/O
net (fo=1, routed) 0.809 9.471 CPU/CPU_Register_File/r2_out0[4]
SLICE_X1Y99 LUT2 (Prop_lut2_I0_O) 0.356 9.827 r CPU/CPU_Register_File/EX_reg_data_2[4]_i_1/O
net (fo=1, routed) 0.000 9.827 CPU/CPU_ID_EX/ID_reg_data_2[4]
SLICE_X1Y99 FDRE r CPU/CPU_ID_EX/EX_reg_data_2_reg[4]/D
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
10.000 10.000 r
E3 0.000 10.000 r clk (IN)
net (fo=0) 0.000 10.000 clk
E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r clk_IBUF_inst/O
net (fo=1, routed) 1.920 13.331 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 1.606 15.029 CPU/CPU_ID_EX/clk_IBUF_BUFG
SLICE_X1Y99 FDRE r CPU/CPU_ID_EX/EX_reg_data_2_reg[4]/C
clock pessimism 0.180 15.209
clock uncertainty -0.035 15.173
SLICE_X1Y99 FDRE (Setup_fdre_C_D) 0.075 15.248 CPU/CPU_ID_EX/EX_reg_data_2_reg[4]
-------------------------------------------------------------------
required time 15.248
arrival time -9.827
-------------------------------------------------------------------
slack 5.421
Slack (MET) : 5.437ns (required time - arrival time)
Source: CPU/CPU_ID_EX/EX_imm_reg[2]/C
(rising edge-triggered cell FDRE clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Destination: CPU/CPU_EX_MEM/MEM_alu_result_reg[3]/D
(rising edge-triggered cell FDRE clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Path Group: sys_clk_pin
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (sys_clk_pin [email protected] - sys_clk_pin [email protected])
Data Path Delay: 4.320ns (logic 1.492ns (34.536%) route 2.828ns (65.464%))
Logic Levels: 3 (CARRY4=1 LUT4=1 LUT5=1)
Clock Path Skew: -0.103ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.029ns = ( 15.029 - 10.000 )
Source Clock Delay (SCD): 5.311ns
Clock Pessimism Removal (CPR): 0.180ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
0.000 0.000 r
E3 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 clk
E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O
net (fo=1, routed) 2.025 3.506 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 1.709 5.311 CPU/CPU_ID_EX/clk_IBUF_BUFG
SLICE_X5Y101 FDRE r CPU/CPU_ID_EX/EX_imm_reg[2]/C
------------------------------------------------------------------- -------------------
SLICE_X5Y101 FDRE (Prop_fdre_C_Q) 0.456 5.767 r CPU/CPU_ID_EX/EX_imm_reg[2]/Q
net (fo=11, routed) 1.148 6.915 CPU/CPU_ID_EX/Q[1]
SLICE_X3Y98 LUT4 (Prop_lut4_I1_O) 0.124 7.039 r CPU/CPU_ID_EX/temp0_carry_i_4/O
net (fo=1, routed) 0.000 7.039 CPU/CPU_ALU/S[0]
SLICE_X3Y98 CARRY4 (Prop_carry4_S[0]_O[3])
0.606 7.645 r CPU/CPU_ALU/temp0_carry/O[3]
net (fo=1, routed) 0.426 8.070 CPU/CPU_ID_EX/data0[3]
SLICE_X2Y98 LUT5 (Prop_lut5_I3_O) 0.306 8.376 r CPU/CPU_ID_EX/MEM_alu_result[3]_i_1/O
net (fo=2, routed) 1.255 9.631 CPU/CPU_EX_MEM/EX_alu_result[3]
SLICE_X3Y99 FDRE r CPU/CPU_EX_MEM/MEM_alu_result_reg[3]/D
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
10.000 10.000 r
E3 0.000 10.000 r clk (IN)
net (fo=0) 0.000 10.000 clk
E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r clk_IBUF_inst/O
net (fo=1, routed) 1.920 13.331 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 1.606 15.029 CPU/CPU_EX_MEM/clk_IBUF_BUFG
SLICE_X3Y99 FDRE r CPU/CPU_EX_MEM/MEM_alu_result_reg[3]/C
clock pessimism 0.180 15.209
clock uncertainty -0.035 15.173
SLICE_X3Y99 FDRE (Setup_fdre_C_D) -0.105 15.068 CPU/CPU_EX_MEM/MEM_alu_result_reg[3]
-------------------------------------------------------------------
required time 15.068
arrival time -9.631
-------------------------------------------------------------------
slack 5.437
Slack (MET) : 5.653ns (required time - arrival time)
Source: CPU/CPU_ID_EX/EX_imm_reg[2]/C
(rising edge-triggered cell FDRE clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Destination: CPU/CPU_EX_MEM/MEM_alu_result_reg[5]/D
(rising edge-triggered cell FDRE clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Path Group: sys_clk_pin
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (sys_clk_pin [email protected] - sys_clk_pin [email protected])
Data Path Delay: 4.239ns (logic 1.749ns (41.255%) route 2.490ns (58.745%))
Logic Levels: 4 (CARRY4=2 LUT4=1 LUT6=1)
Clock Path Skew: -0.025ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.010ns = ( 15.010 - 10.000 )
Source Clock Delay (SCD): 5.311ns
Clock Pessimism Removal (CPR): 0.276ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
0.000 0.000 r
E3 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 clk
E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O
net (fo=1, routed) 2.025 3.506 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 1.709 5.311 CPU/CPU_ID_EX/clk_IBUF_BUFG
SLICE_X5Y101 FDRE r CPU/CPU_ID_EX/EX_imm_reg[2]/C
------------------------------------------------------------------- -------------------
SLICE_X5Y101 FDRE (Prop_fdre_C_Q) 0.456 5.767 r CPU/CPU_ID_EX/EX_imm_reg[2]/Q
net (fo=11, routed) 1.148 6.915 CPU/CPU_ID_EX/Q[1]
SLICE_X3Y98 LUT4 (Prop_lut4_I1_O) 0.124 7.039 r CPU/CPU_ID_EX/temp0_carry_i_4/O
net (fo=1, routed) 0.000 7.039 CPU/CPU_ALU/S[0]
SLICE_X3Y98 CARRY4 (Prop_carry4_S[0]_CO[3])
0.532 7.571 r CPU/CPU_ALU/temp0_carry/CO[3]
net (fo=1, routed) 0.000 7.571 CPU/CPU_ALU/temp0_carry_n_0
SLICE_X3Y99 CARRY4 (Prop_carry4_CI_O[1])
0.334 7.905 r CPU/CPU_ALU/temp0_carry__0/O[1]
net (fo=1, routed) 0.568 8.472 CPU/CPU_ID_EX/data0[5]
SLICE_X0Y99 LUT6 (Prop_lut6_I4_O) 0.303 8.775 r CPU/CPU_ID_EX/MEM_alu_result[5]_i_1/O
net (fo=2, routed) 0.775 9.551 CPU/CPU_EX_MEM/EX_alu_result[5]
SLICE_X5Y100 FDRE r CPU/CPU_EX_MEM/MEM_alu_result_reg[5]/D
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
10.000 10.000 r
E3 0.000 10.000 r clk (IN)
net (fo=0) 0.000 10.000 clk
E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r clk_IBUF_inst/O
net (fo=1, routed) 1.920 13.331 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 1.588 15.010 CPU/CPU_EX_MEM/clk_IBUF_BUFG
SLICE_X5Y100 FDRE r CPU/CPU_EX_MEM/MEM_alu_result_reg[5]/C
clock pessimism 0.276 15.286
clock uncertainty -0.035 15.251
SLICE_X5Y100 FDRE (Setup_fdre_C_D) -0.047 15.204 CPU/CPU_EX_MEM/MEM_alu_result_reg[5]
-------------------------------------------------------------------
required time 15.204
arrival time -9.551
-------------------------------------------------------------------
slack 5.653
Slack (MET) : 5.792ns (required time - arrival time)
Source: CPU/CPU_ID_EX/EX_imm_reg[2]/C
(rising edge-triggered cell FDRE clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Destination: CPU/CPU_EX_MEM/MEM_alu_result_reg[2]/D
(rising edge-triggered cell FDRE clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Path Group: sys_clk_pin
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (sys_clk_pin [email protected] - sys_clk_pin [email protected])
Data Path Delay: 4.055ns (logic 1.429ns (35.241%) route 2.626ns (64.759%))
Logic Levels: 3 (CARRY4=1 LUT4=1 LUT6=1)
Clock Path Skew: -0.025ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.010ns = ( 15.010 - 10.000 )
Source Clock Delay (SCD): 5.311ns
Clock Pessimism Removal (CPR): 0.276ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
0.000 0.000 r
E3 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 clk
E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O
net (fo=1, routed) 2.025 3.506 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 1.709 5.311 CPU/CPU_ID_EX/clk_IBUF_BUFG
SLICE_X5Y101 FDRE r CPU/CPU_ID_EX/EX_imm_reg[2]/C
------------------------------------------------------------------- -------------------
SLICE_X5Y101 FDRE (Prop_fdre_C_Q) 0.456 5.767 r CPU/CPU_ID_EX/EX_imm_reg[2]/Q
net (fo=11, routed) 1.148 6.915 CPU/CPU_ID_EX/Q[1]
SLICE_X3Y98 LUT4 (Prop_lut4_I1_O) 0.124 7.039 r CPU/CPU_ID_EX/temp0_carry_i_4/O
net (fo=1, routed) 0.000 7.039 CPU/CPU_ALU/S[0]
SLICE_X3Y98 CARRY4 (Prop_carry4_S[0]_O[2])
0.547 7.586 r CPU/CPU_ALU/temp0_carry/O[2]
net (fo=1, routed) 0.788 8.374 CPU/CPU_ID_EX/data0[2]
SLICE_X0Y100 LUT6 (Prop_lut6_I4_O) 0.302 8.676 r CPU/CPU_ID_EX/MEM_alu_result[2]_i_1/O
net (fo=2, routed) 0.690 9.366 CPU/CPU_EX_MEM/EX_alu_result[2]
SLICE_X5Y100 FDRE r CPU/CPU_EX_MEM/MEM_alu_result_reg[2]/D
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
10.000 10.000 r
E3 0.000 10.000 r clk (IN)
net (fo=0) 0.000 10.000 clk
E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r clk_IBUF_inst/O
net (fo=1, routed) 1.920 13.331 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 1.588 15.010 CPU/CPU_EX_MEM/clk_IBUF_BUFG
SLICE_X5Y100 FDRE r CPU/CPU_EX_MEM/MEM_alu_result_reg[2]/C
clock pessimism 0.276 15.286
clock uncertainty -0.035 15.251
SLICE_X5Y100 FDRE (Setup_fdre_C_D) -0.093 15.158 CPU/CPU_EX_MEM/MEM_alu_result_reg[2]
-------------------------------------------------------------------
required time 15.158
arrival time -9.366
-------------------------------------------------------------------
slack 5.792
Slack (MET) : 5.814ns (required time - arrival time)
Source: CPU/CPU_ID_EX/EX_imm_reg[2]/C
(rising edge-triggered cell FDRE clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Destination: CPU/CPU_EX_MEM/MEM_alu_result_reg[6]/D
(rising edge-triggered cell FDRE clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Path Group: sys_clk_pin
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (sys_clk_pin [email protected] - sys_clk_pin [email protected])
Data Path Delay: 4.062ns (logic 1.653ns (40.693%) route 2.409ns (59.307%))
Logic Levels: 4 (CARRY4=2 LUT4=1 LUT6=1)
Clock Path Skew: -0.022ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.010ns = ( 15.010 - 10.000 )
Source Clock Delay (SCD): 5.311ns
Clock Pessimism Removal (CPR): 0.279ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
0.000 0.000 r
E3 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 clk
E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O
net (fo=1, routed) 2.025 3.506 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 1.709 5.311 CPU/CPU_ID_EX/clk_IBUF_BUFG
SLICE_X5Y101 FDRE r CPU/CPU_ID_EX/EX_imm_reg[2]/C
------------------------------------------------------------------- -------------------
SLICE_X5Y101 FDRE (Prop_fdre_C_Q) 0.456 5.767 r CPU/CPU_ID_EX/EX_imm_reg[2]/Q
net (fo=11, routed) 1.148 6.915 CPU/CPU_ID_EX/Q[1]
SLICE_X3Y98 LUT4 (Prop_lut4_I1_O) 0.124 7.039 r CPU/CPU_ID_EX/temp0_carry_i_4/O
net (fo=1, routed) 0.000 7.039 CPU/CPU_ALU/S[0]
SLICE_X3Y98 CARRY4 (Prop_carry4_S[0]_CO[3])
0.532 7.571 r CPU/CPU_ALU/temp0_carry/CO[3]
net (fo=1, routed) 0.000 7.571 CPU/CPU_ALU/temp0_carry_n_0
SLICE_X3Y99 CARRY4 (Prop_carry4_CI_O[2])
0.239 7.810 r CPU/CPU_ALU/temp0_carry__0/O[2]
net (fo=1, routed) 0.766 8.576 CPU/CPU_ID_EX/data0[6]
SLICE_X3Y100 LUT6 (Prop_lut6_I4_O) 0.302 8.878 r CPU/CPU_ID_EX/MEM_alu_result[6]_i_1/O
net (fo=2, routed) 0.495 9.373 CPU/CPU_EX_MEM/EX_alu_result[6]
SLICE_X4Y101 FDRE r CPU/CPU_EX_MEM/MEM_alu_result_reg[6]/D
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
10.000 10.000 r
E3 0.000 10.000 r clk (IN)
net (fo=0) 0.000 10.000 clk
E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r clk_IBUF_inst/O
net (fo=1, routed) 1.920 13.331 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 1.588 15.010 CPU/CPU_EX_MEM/clk_IBUF_BUFG
SLICE_X4Y101 FDRE r CPU/CPU_EX_MEM/MEM_alu_result_reg[6]/C
clock pessimism 0.279 15.289
clock uncertainty -0.035 15.254
SLICE_X4Y101 FDRE (Setup_fdre_C_D) -0.067 15.187 CPU/CPU_EX_MEM/MEM_alu_result_reg[6]
-------------------------------------------------------------------
required time 15.187
arrival time -9.373
-------------------------------------------------------------------
slack 5.814
Slack (MET) : 5.829ns (required time - arrival time)
Source: CPU/CPU_IF_ID/ID_instruction_reg[14]/C
(rising edge-triggered cell FDRE clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Destination: CPU/CPU_ID_EX/EX_reg_data_2_reg[5]/D
(rising edge-triggered cell FDRE clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Path Group: sys_clk_pin
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (sys_clk_pin [email protected] - sys_clk_pin [email protected])
Data Path Delay: 4.108ns (logic 0.919ns (22.372%) route 3.189ns (77.628%))
Logic Levels: 3 (LUT2=1 LUT5=1 RAMD32=1)
Clock Path Skew: -0.103ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.029ns = ( 15.029 - 10.000 )
Source Clock Delay (SCD): 5.311ns
Clock Pessimism Removal (CPR): 0.180ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
0.000 0.000 r
E3 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 clk
E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O
net (fo=1, routed) 2.025 3.506 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 1.709 5.311 CPU/CPU_IF_ID/clk_IBUF_BUFG
SLICE_X6Y100 FDRE r CPU/CPU_IF_ID/ID_instruction_reg[14]/C
------------------------------------------------------------------- -------------------
SLICE_X6Y100 FDRE (Prop_fdre_C_Q) 0.518 5.829 r CPU/CPU_IF_ID/ID_instruction_reg[14]/Q
net (fo=8, routed) 1.092 6.921 CPU/CPU_IF_ID/ID_instruction[14]
SLICE_X4Y100 LUT5 (Prop_lut5_I2_O) 0.124 7.045 r CPU/CPU_IF_ID/registers_reg_r2_0_3_0_5_i_1/O
net (fo=8, routed) 1.464 8.509 CPU/CPU_Register_File/registers_reg_r2_0_3_0_5/ADDRC0
SLICE_X2Y99 RAMD32 (Prop_ramd32_RADR0_O)
0.124 8.633 r CPU/CPU_Register_File/registers_reg_r2_0_3_0_5/RAMC_D1/O
net (fo=1, routed) 0.633 9.266 CPU/CPU_Register_File/r2_out0[5]
SLICE_X1Y99 LUT2 (Prop_lut2_I0_O) 0.153 9.419 r CPU/CPU_Register_File/EX_reg_data_2[5]_i_1/O
net (fo=1, routed) 0.000 9.419 CPU/CPU_ID_EX/ID_reg_data_2[5]
SLICE_X1Y99 FDRE r CPU/CPU_ID_EX/EX_reg_data_2_reg[5]/D
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
10.000 10.000 r
E3 0.000 10.000 r clk (IN)
net (fo=0) 0.000 10.000 clk
E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r clk_IBUF_inst/O
net (fo=1, routed) 1.920 13.331 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 1.606 15.029 CPU/CPU_ID_EX/clk_IBUF_BUFG
SLICE_X1Y99 FDRE r CPU/CPU_ID_EX/EX_reg_data_2_reg[5]/C
clock pessimism 0.180 15.209
clock uncertainty -0.035 15.173
SLICE_X1Y99 FDRE (Setup_fdre_C_D) 0.075 15.248 CPU/CPU_ID_EX/EX_reg_data_2_reg[5]
-------------------------------------------------------------------
required time 15.248
arrival time -9.419
-------------------------------------------------------------------
slack 5.829
Slack (MET) : 6.002ns (required time - arrival time)
Source: CPU/CPU_IF_ID/ID_instruction_reg[14]/C
(rising edge-triggered cell FDRE clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Destination: CPU/CPU_ID_EX/EX_reg_data_2_reg[6]/D
(rising edge-triggered cell FDRE clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Path Group: sys_clk_pin
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (sys_clk_pin [email protected] - sys_clk_pin [email protected])
Data Path Delay: 3.955ns (logic 1.120ns (28.322%) route 2.835ns (71.678%))
Logic Levels: 3 (LUT2=1 LUT5=1 RAMD32=1)
Clock Path Skew: -0.040ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.012ns = ( 15.012 - 10.000 )
Source Clock Delay (SCD): 5.311ns
Clock Pessimism Removal (CPR): 0.259ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
0.000 0.000 r
E3 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 clk
E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O
net (fo=1, routed) 2.025 3.506 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 1.709 5.311 CPU/CPU_IF_ID/clk_IBUF_BUFG
SLICE_X6Y100 FDRE r CPU/CPU_IF_ID/ID_instruction_reg[14]/C
------------------------------------------------------------------- -------------------
SLICE_X6Y100 FDRE (Prop_fdre_C_Q) 0.518 5.829 r CPU/CPU_IF_ID/ID_instruction_reg[14]/Q
net (fo=8, routed) 1.092 6.921 CPU/CPU_IF_ID/ID_instruction[14]
SLICE_X4Y100 LUT5 (Prop_lut5_I2_O) 0.124 7.045 r CPU/CPU_IF_ID/registers_reg_r2_0_3_0_5_i_1/O
net (fo=8, routed) 1.159 8.204 CPU/CPU_Register_File/registers_reg_r2_0_3_6_7/DPRA0
SLICE_X2Y101 RAMD32 (Prop_ramd32_RADR0_O)
0.150 8.354 r CPU/CPU_Register_File/registers_reg_r2_0_3_6_7/DP/O
net (fo=1, routed) 0.584 8.938 CPU/CPU_Register_File/r2_out0[6]
SLICE_X1Y100 LUT2 (Prop_lut2_I0_O) 0.328 9.266 r CPU/CPU_Register_File/EX_reg_data_2[6]_i_1/O
net (fo=1, routed) 0.000 9.266 CPU/CPU_ID_EX/ID_reg_data_2[6]
SLICE_X1Y100 FDRE r CPU/CPU_ID_EX/EX_reg_data_2_reg[6]/D
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
10.000 10.000 r
E3 0.000 10.000 r clk (IN)
net (fo=0) 0.000 10.000 clk
E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r clk_IBUF_inst/O
net (fo=1, routed) 1.920 13.331 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 1.590 15.012 CPU/CPU_ID_EX/clk_IBUF_BUFG
SLICE_X1Y100 FDRE r CPU/CPU_ID_EX/EX_reg_data_2_reg[6]/C
clock pessimism 0.259 15.271
clock uncertainty -0.035 15.236
SLICE_X1Y100 FDRE (Setup_fdre_C_D) 0.032 15.268 CPU/CPU_ID_EX/EX_reg_data_2_reg[6]
-------------------------------------------------------------------
required time 15.268
arrival time -9.266
-------------------------------------------------------------------
slack 6.002
Slack (MET) : 6.015ns (required time - arrival time)
Source: CPU/CPU_IF_ID/ID_instruction_reg[14]/C
(rising edge-triggered cell FDRE clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Destination: CPU/CPU_ID_EX/EX_reg_data_2_reg[7]/D
(rising edge-triggered cell FDRE clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Path Group: sys_clk_pin
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (sys_clk_pin [email protected] - sys_clk_pin [email protected])
Data Path Delay: 3.984ns (logic 0.915ns (22.965%) route 3.069ns (77.035%))
Logic Levels: 3 (LUT2=1 LUT5=1 RAMD32=1)
Clock Path Skew: -0.040ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.012ns = ( 15.012 - 10.000 )
Source Clock Delay (SCD): 5.311ns
Clock Pessimism Removal (CPR): 0.259ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
0.000 0.000 r
E3 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 clk
E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O
net (fo=1, routed) 2.025 3.506 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 1.709 5.311 CPU/CPU_IF_ID/clk_IBUF_BUFG
SLICE_X6Y100 FDRE r CPU/CPU_IF_ID/ID_instruction_reg[14]/C
------------------------------------------------------------------- -------------------
SLICE_X6Y100 FDRE (Prop_fdre_C_Q) 0.518 5.829 r CPU/CPU_IF_ID/ID_instruction_reg[14]/Q
net (fo=8, routed) 1.092 6.921 CPU/CPU_IF_ID/ID_instruction[14]
SLICE_X4Y100 LUT5 (Prop_lut5_I2_O) 0.124 7.045 r CPU/CPU_IF_ID/registers_reg_r2_0_3_0_5_i_1/O
net (fo=8, routed) 1.159 8.204 CPU/CPU_Register_File/registers_reg_r2_0_3_6_7__0/DPRA0
SLICE_X2Y101 RAMD32 (Prop_ramd32_RADR0_O)
0.124 8.328 r CPU/CPU_Register_File/registers_reg_r2_0_3_6_7__0/DP/O
net (fo=1, routed) 0.819 9.147 CPU/CPU_Register_File/r2_out0[7]
SLICE_X1Y100 LUT2 (Prop_lut2_I0_O) 0.149 9.296 r CPU/CPU_Register_File/EX_reg_data_2[7]_i_1/O
net (fo=1, routed) 0.000 9.296 CPU/CPU_ID_EX/ID_reg_data_2[7]
SLICE_X1Y100 FDRE r CPU/CPU_ID_EX/EX_reg_data_2_reg[7]/D
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
10.000 10.000 r
E3 0.000 10.000 r clk (IN)
net (fo=0) 0.000 10.000 clk
E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r clk_IBUF_inst/O
net (fo=1, routed) 1.920 13.331 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 1.590 15.012 CPU/CPU_ID_EX/clk_IBUF_BUFG
SLICE_X1Y100 FDRE r CPU/CPU_ID_EX/EX_reg_data_2_reg[7]/C
clock pessimism 0.259 15.271
clock uncertainty -0.035 15.236
SLICE_X1Y100 FDRE (Setup_fdre_C_D) 0.075 15.311 CPU/CPU_ID_EX/EX_reg_data_2_reg[7]
-------------------------------------------------------------------
required time 15.311
arrival time -9.296
-------------------------------------------------------------------
slack 6.015
Slack (MET) : 6.158ns (required time - arrival time)
Source: CPU/CPU_IF_ID/ID_instruction_reg[14]/C
(rising edge-triggered cell FDRE clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Destination: CPU/CPU_ID_EX/EX_reg_data_2_reg[2]/D
(rising edge-triggered cell FDRE clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Path Group: sys_clk_pin
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (sys_clk_pin [email protected] - sys_clk_pin [email protected])
Data Path Delay: 3.779ns (logic 1.170ns (30.960%) route 2.609ns (69.040%))
Logic Levels: 3 (LUT2=1 LUT5=1 RAMD32=1)
Clock Path Skew: -0.103ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.029ns = ( 15.029 - 10.000 )
Source Clock Delay (SCD): 5.311ns
Clock Pessimism Removal (CPR): 0.180ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
0.000 0.000 r
E3 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 clk
E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O
net (fo=1, routed) 2.025 3.506 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 1.709 5.311 CPU/CPU_IF_ID/clk_IBUF_BUFG
SLICE_X6Y100 FDRE r CPU/CPU_IF_ID/ID_instruction_reg[14]/C
------------------------------------------------------------------- -------------------
SLICE_X6Y100 FDRE (Prop_fdre_C_Q) 0.518 5.829 r CPU/CPU_IF_ID/ID_instruction_reg[14]/Q
net (fo=8, routed) 1.092 6.921 CPU/CPU_IF_ID/ID_instruction[14]
SLICE_X4Y100 LUT5 (Prop_lut5_I2_O) 0.124 7.045 r CPU/CPU_IF_ID/registers_reg_r2_0_3_0_5_i_1/O
net (fo=8, routed) 0.868 7.913 CPU/CPU_Register_File/registers_reg_r2_0_3_0_5/ADDRB0
SLICE_X2Y99 RAMD32 (Prop_ramd32_RADR0_O)
0.152 8.065 r CPU/CPU_Register_File/registers_reg_r2_0_3_0_5/RAMB/O
net (fo=1, routed) 0.649 8.714 CPU/CPU_Register_File/r2_out0[2]
SLICE_X1Y99 LUT2 (Prop_lut2_I0_O) 0.376 9.090 r CPU/CPU_Register_File/EX_reg_data_2[2]_i_1/O
net (fo=1, routed) 0.000 9.090 CPU/CPU_ID_EX/ID_reg_data_2[2]
SLICE_X1Y99 FDRE r CPU/CPU_ID_EX/EX_reg_data_2_reg[2]/D
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
10.000 10.000 r
E3 0.000 10.000 r clk (IN)
net (fo=0) 0.000 10.000 clk
E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r clk_IBUF_inst/O
net (fo=1, routed) 1.920 13.331 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 1.606 15.029 CPU/CPU_ID_EX/clk_IBUF_BUFG
SLICE_X1Y99 FDRE r CPU/CPU_ID_EX/EX_reg_data_2_reg[2]/C
clock pessimism 0.180 15.209
clock uncertainty -0.035 15.173
SLICE_X1Y99 FDRE (Setup_fdre_C_D) 0.075 15.248 CPU/CPU_ID_EX/EX_reg_data_2_reg[2]
-------------------------------------------------------------------
required time 15.248
arrival time -9.090
-------------------------------------------------------------------
slack 6.158
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.051ns (arrival time - required time)
Source: CPU/CPU_MEM_WB/WB_alu_result_reg[0]/C
(rising edge-triggered cell FDRE clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Destination: CPU/CPU_Register_File/registers_reg_r1_0_3_0_5/RAMA/I
(rising edge-triggered cell RAMD32 clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Path Group: sys_clk_pin
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (sys_clk_pin [email protected] - sys_clk_pin [email protected])
Data Path Delay: 0.211ns (logic 0.141ns (66.741%) route 0.070ns (33.259%))
Logic Levels: 0
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.037ns
Source Clock Delay (SCD): 1.518ns
Clock Pessimism Removal (CPR): 0.505ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
0.000 0.000 r
E3 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 clk
E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r clk_IBUF_inst/O
net (fo=1, routed) 0.644 0.894 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 0.599 1.518 CPU/CPU_MEM_WB/clk_IBUF_BUFG
SLICE_X3Y100 FDRE r CPU/CPU_MEM_WB/WB_alu_result_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X3Y100 FDRE (Prop_fdre_C_Q) 0.141 1.659 r CPU/CPU_MEM_WB/WB_alu_result_reg[0]/Q
net (fo=2, routed) 0.070 1.730 CPU/CPU_Register_File/registers_reg_r1_0_3_0_5/DIA0
SLICE_X2Y100 RAMD32 r CPU/CPU_Register_File/registers_reg_r1_0_3_0_5/RAMA/I
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
0.000 0.000 r
E3 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 clk
E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r clk_IBUF_inst/O
net (fo=1, routed) 0.699 1.136 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 0.872 2.037 CPU/CPU_Register_File/registers_reg_r1_0_3_0_5/WCLK
SLICE_X2Y100 RAMD32 r CPU/CPU_Register_File/registers_reg_r1_0_3_0_5/RAMA/CLK
clock pessimism -0.505 1.531
SLICE_X2Y100 RAMD32 (Hold_ramd32_CLK_I)
0.147 1.678 CPU/CPU_Register_File/registers_reg_r1_0_3_0_5/RAMA
-------------------------------------------------------------------
required time -1.678
arrival time 1.730
-------------------------------------------------------------------
slack 0.051
Slack (MET) : 0.059ns (arrival time - required time)
Source: CPU/CPU_MEM_WB/WB_rd_reg[0]/C
(rising edge-triggered cell FDRE clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Destination: CPU/CPU_Register_File/registers_reg_r2_0_3_0_5/RAMA/WADR0
(rising edge-triggered cell RAMD32 clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Path Group: sys_clk_pin
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (sys_clk_pin [email protected] - sys_clk_pin [email protected])
Data Path Delay: 0.409ns (logic 0.141ns (34.505%) route 0.268ns (65.495%))
Logic Levels: 0
Clock Path Skew: 0.040ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.043ns
Source Clock Delay (SCD): 1.523ns
Clock Pessimism Removal (CPR): 0.479ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
0.000 0.000 r
E3 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 clk
E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r clk_IBUF_inst/O
net (fo=1, routed) 0.644 0.894 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 0.604 1.523 CPU/CPU_MEM_WB/clk_IBUF_BUFG
SLICE_X4Y99 FDRE r CPU/CPU_MEM_WB/WB_rd_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X4Y99 FDRE (Prop_fdre_C_Q) 0.141 1.664 r CPU/CPU_MEM_WB/WB_rd_reg[0]/Q
net (fo=29, routed) 0.268 1.932 CPU/CPU_Register_File/registers_reg_r2_0_3_0_5/ADDRD0
SLICE_X2Y99 RAMD32 r CPU/CPU_Register_File/registers_reg_r2_0_3_0_5/RAMA/WADR0
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
0.000 0.000 r
E3 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 clk
E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r clk_IBUF_inst/O
net (fo=1, routed) 0.699 1.136 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 0.878 2.043 CPU/CPU_Register_File/registers_reg_r2_0_3_0_5/WCLK
SLICE_X2Y99 RAMD32 r CPU/CPU_Register_File/registers_reg_r2_0_3_0_5/RAMA/CLK
clock pessimism -0.479 1.563
SLICE_X2Y99 RAMD32 (Hold_ramd32_CLK_WADR0)
0.310 1.873 CPU/CPU_Register_File/registers_reg_r2_0_3_0_5/RAMA
-------------------------------------------------------------------
required time -1.873
arrival time 1.932
-------------------------------------------------------------------
slack 0.059
Slack (MET) : 0.059ns (arrival time - required time)
Source: CPU/CPU_MEM_WB/WB_rd_reg[0]/C
(rising edge-triggered cell FDRE clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Destination: CPU/CPU_Register_File/registers_reg_r2_0_3_0_5/RAMA_D1/WADR0
(rising edge-triggered cell RAMD32 clocked by sys_clk_pin {[email protected] [email protected] period=10.000ns})
Path Group: sys_clk_pin
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (sys_clk_pin [email protected] - sys_clk_pin [email protected])
Data Path Delay: 0.409ns (logic 0.141ns (34.505%) route 0.268ns (65.495%))
Logic Levels: 0
Clock Path Skew: 0.040ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.043ns
Source Clock Delay (SCD): 1.523ns
Clock Pessimism Removal (CPR): 0.479ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
0.000 0.000 r
E3 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 clk
E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r clk_IBUF_inst/O
net (fo=1, routed) 0.644 0.894 clk_IBUF
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r clk_IBUF_BUFG_inst/O
net (fo=130, routed) 0.604 1.523 CPU/CPU_MEM_WB/clk_IBUF_BUFG
SLICE_X4Y99 FDRE r CPU/CPU_MEM_WB/WB_rd_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X4Y99 FDRE (Prop_fdre_C_Q) 0.141 1.664 r CPU/CPU_MEM_WB/WB_rd_reg[0]/Q
net (fo=29, routed) 0.268 1.932 CPU/CPU_Register_File/registers_reg_r2_0_3_0_5/ADDRD0
SLICE_X2Y99 RAMD32 r CPU/CPU_Register_File/registers_reg_r2_0_3_0_5/RAMA_D1/WADR0
------------------------------------------------------------------- -------------------
(clock sys_clk_pin rise edge)
0.000 0.000 r
E3 0.000 0.000 r clk (IN)